PIC18F4523-I/PT Microchip Technology, PIC18F4523-I/PT Datasheet - Page 108
![IC PIC MCU FLASH 16KX16 44TQFP](/photos/6/82/68251/c04-076_pt_sml.jpg)
PIC18F4523-I/PT
Manufacturer Part Number
PIC18F4523-I/PT
Description
IC PIC MCU FLASH 16KX16 44TQFP
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC18F2221-ISO.pdf
(46 pages)
2.PIC18F2423-ISP.pdf
(54 pages)
3.PIC18F2423-ISP.pdf
(8 pages)
4.PIC18F2423-ISP.pdf
(34 pages)
5.PIC18F2523-ISO.pdf
(392 pages)
Specifications of PIC18F4523-I/PT
Program Memory Type
FLASH
Program Memory Size
32KB (16K x 16)
Package / Case
44-TQFP, 44-VQFP
Core Processor
PIC
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, HLVD, POR, PWM, WDT
Number Of I /o
36
Eeprom Size
256 x 8
Ram Size
1.5K x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 13x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
1.5 KB
Interface Type
EUSART/I2C/MSSP/SPI
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
36
Number Of Timers
4
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, 53275-917, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DV164136, DM163022
Minimum Operating Temperature
- 40 C
On-chip Adc
13-ch x 12-bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
AC164305 - MODULE SKT FOR PM3 44TQFP444-1001 - DEMO BOARD FOR PICMICRO MCUAC164020 - MODULE SKT PROMATEII 44TQFP
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
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- PIC18F2221-ISO PDF datasheet
- PIC18F2423-ISP PDF datasheet #2
- PIC18F2423-ISP PDF datasheet #3
- PIC18F2423-ISP PDF datasheet #4
- PIC18F2523-ISO PDF datasheet #5
- Current page: 108 of 392
- Download datasheet (7Mb)
PIC18F2423/2523/4423/4523
TABLE 10-1:
DS39755B-page 106
RA0/AN0
RA1/AN1
RA2/AN2/
V
RA3/AN3/V
RA4/T0CKI/C1OUT
RA5/AN4/SS/
HLVDIN/C2OUT
OSC2/CLKO/RA6
OSC1/CLKI/RA7
Legend:
REF
-/CV
Pin
REF
REF
DIG = Digital level output; TTL = TTL input buffer; ST = Schmitt Trigger input buffer; ANA = Analog level input/output;
x = Don’t care (TRIS bit does not affect port direction or is overridden for this option).
+
PORTA I/O SUMMARY
Function
HLVDIN
C1OUT
C2OUT
CV
V
T0CKI
OSC2
CLKO
OSC1
V
CLKI
RA0
AN0
RA1
AN1
RA2
AN2
RA3
AN3
RA4
RA5
AN4
RA6
RA7
REF
REF
SS
REF
+
-
Setting
TRIS
0
1
1
0
1
1
0
1
1
1
x
0
1
1
1
0
1
1
0
0
1
1
1
1
0
x
x
0
1
x
x
0
1
I/O
O
O
O
O
O
O
O
O
O
O
O
O
O
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
Type
ANA
ANA
ANA
ANA
ANA
ANA
ANA
ANA
ANA
ANA
ANA
ANA
DIG
TTL
DIG
TTL
DIG
TTL
DIG
TTL
DIG
DIG
DIG
TTL
TTL
DIG
DIG
DIG
TTL
DIG
TTL
I/O
ST
ST
Preliminary
LATA<0> data output; not affected by analog input.
PORTA<0> data input; disabled when analog input enabled.
A/D input channel 0 and Comparator C1- input. Default input
configuration on POR; does not affect digital output.
LATA<1> data output; not affected by analog input.
PORTA<1> data input; disabled when analog input enabled.
A/D input channel 1 and Comparator C2- input. Default input
configuration on POR; does not affect digital output.
LATA<2> data output; not affected by analog input. Disabled when
CV
PORTA<2> data input. Disabled when analog functions enabled;
disabled when CV
A/D input channel 2 and Comparator C2+ input. Default input
configuration on POR; not affected by analog output.
A/D and comparator voltage reference low input.
Comparator voltage reference output. Enabling this feature disables
digital I/O.
LATA<3> data output; not affected by analog input.
PORTA<3> data input; disabled when analog input enabled.
A/D input channel 3 and Comparator C1+ input. Default input
configuration on POR.
A/D and comparator voltage reference high input.
LATA<4> data output.
PORTA<4> data input; default configuration on POR.
Timer0 clock input.
Comparator 1 output; takes priority over port data.
LATA<5> data output; not affected by analog input.
PORTA<5> data input; disabled when analog input enabled.
A/D input channel 4. Default configuration on POR.
Slave select input for MSSP (MSSP module).
High/Low-Voltage Detect external trip point input.
Comparator 2 output; takes priority over port data.
Main oscillator feedback output connection (XT, HS and LP modes).
System cycle clock output (F
modes.
LATA<6> data output. Enabled in RCIO, INTIO2 and ECIO modes only.
PORTA<6> data input. Enabled in RCIO, INTIO2 and ECIO modes
only.
Main oscillator input connection.
Main clock input connection.
LATA<7> data output. Disabled in external oscillator modes.
PORTA<7> data input. Disabled in external oscillator modes.
REF
output enabled.
REF
output enabled.
OSC
Description
/4) in RC, INTIO1 and EC Oscillator
© 2007 Microchip Technology Inc.
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