PIC18F4523-I/PT Microchip Technology, PIC18F4523-I/PT Datasheet - Page 386

• Manufacturer Part Number: PIC18F4523-I/PT
• Description: IC PIC MCU FLASH 16KX16 44TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F4523-I/PT

• Program Memory Type: FLASH
• Program Memory Size: 32KB (16K x 16)
• Package / Case: 44-TQFP, 44-VQFP
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 36
• Eeprom Size: 256 x 8
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 13x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 1.5 KB
• Interface Type: EUSART/I2C/MSSP/SPI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 36
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, 53275-917, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DV164136, DM163022
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 13-ch x 12-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC164305 - MODULE SKT FOR PM3 44TQFP444-1001 - DEMO BOARD FOR PICMICRO MCUAC164020 - MODULE SKT PROMATEII 44TQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PIC18F2423/2523/4423/4523
Serial Clock, SCK ............................................................. 161
Serial Data In (SDI) .......................................................... 161
Serial Data Out (SDO) ..................................................... 161
Serial Peripheral Interface. See SPI Mode.
SETF ................................................................................ 305
Single-Supply ICSP Programming.
Slave Select (SS) ............................................................. 161
SLEEP .............................................................................. 306
Sleep
Software Simulator (MPLAB SIM) .................................... 322
Special Event Trigger. See Compare (ECCP Mode).
Special Features of the CPU ............................................ 253
Special Function Registers ................................................ 63
SPI Mode (MSSP)
SS .................................................................................... 161
SSPOV ............................................................................. 195
SSPOV Status Flag .......................................................... 195
SSPSTAT Register
Stack Full/Underflow Resets .............................................. 56
SUBFSR ........................................................................... 317
SUBFWB .......................................................................... 306
SUBLW ............................................................................ 307
SUBULNK ........................................................................ 317
SUBWF ............................................................................ 307
SUBWFB .......................................................................... 308
SWAPF ............................................................................ 308
T
Table Pointer Operations (table) ........................................ 76
Table Reads/Table Writes .................................................. 56
TBLRD ............................................................................. 309
TBLWT ............................................................................. 310
Time-out in Various Situations (table) ................................ 45
Timer0 .............................................................................. 123
DS39755B-page 384
OSC1 and OSC2 Pin States ...................................... 31
Map ............................................................................ 63
Associated Registers ............................................... 169
Bus Mode Compatibility ........................................... 169
Effects of a Reset ..................................................... 169
Enabling SPI I/O ...................................................... 165
Master Mode ............................................................ 166
Master/Slave Connection ......................................... 165
Operation ................................................................. 164
Operation in Power-Managed Modes ...................... 169
Serial Clock .............................................................. 161
Serial Data In ........................................................... 161
Serial Data Out ........................................................ 161
Slave Mode .............................................................. 167
Slave Select ............................................................. 161
Slave Select Synchronization .................................. 167
SPI Clock ................................................................. 166
Typical Connection .................................................. 165
R/W Bit ............................................................. 175, 177
Associated Registers ............................................... 125
Interrupt .................................................................... 125
Operation ................................................................. 124
Prescaler .................................................................. 125
Prescaler Assignment (PSA Bit) .............................. 125
Prescaler Select (T0PS2:T0PS0 Bits) ..................... 125
Prescaler. See Prescaler, Timer0.
Reads and Writes in 16-Bit Mode ............................ 124
Source Edge Select (T0SE Bit) ................................ 124
Source Select (T0CS Bit) ......................................... 124
Switching Prescaler Assignment .............................. 125
Preliminary
Timer1 .............................................................................. 127
Timer2 .............................................................................. 133
Timer3 .............................................................................. 135
Timing Diagrams
16-Bit Read/Write Mode .......................................... 129
Associated Registers ............................................... 131
Interrupt ................................................................... 130
Operation ................................................................. 128
Oscillator .......................................................... 127, 129
Overflow Interrupt .................................................... 127
Resetting, Using the CCP
TMR1H Register ...................................................... 127
TMR1L Register ....................................................... 127
Use as a Real-Time Clock ....................................... 130
Associated Registers ............................................... 134
Interrupt ................................................................... 134
Operation ................................................................. 133
Output ...................................................................... 134
PR2 Register ................................................... 144, 149
TMR2 to PR2 Match Interrupt .......................... 144, 149
16-Bit Read/Write Mode .......................................... 137
Associated Registers ............................................... 137
Interrupt ................................................................... 137
Operation ................................................................. 136
Oscillator .......................................................... 135, 137
Overflow Interrupt .................................................... 135
Special Event Trigger (CCP) ................................... 137
TMR3H Register ...................................................... 135
TMR3L Register ....................................................... 135
A/D Conversion ........................................................ 361
Acknowledge Sequence .......................................... 198
Asynchronous Reception ......................................... 218
Asynchronous Transmission .................................... 216
Asynchronous Transmission
Automatic Baud Rate Calculation ............................ 214
Auto-Wake-up Bit (WUE) During
Auto-Wake-up Bit (WUE) During Sleep ................... 219
Baud Rate Generator with Clock Arbitration ............ 192
BRG Overflow Sequence ......................................... 214
BRG Reset Due to SDA Arbitration During
Brown-out Reset (BOR) ........................................... 347
Bus Collision During a Repeated Start
Bus Collision During a Repeated Start
Bus Collision During a Start
Bus Collision During a Stop
Bus Collision During a Stop
Bus Collision During Start
Bus Collision for Transmit and Acknowledge .......... 199
Capture/Compare/PWM (All CCP Modules) ............ 349
CLKO and I/O .......................................................... 346
Clock Synchronization ............................................. 185
Clock/Instruction Cycle .............................................. 57
Layout Considerations ..................................... 130
Special Event Trigger ...................................... 130
(Back-to-Back) ................................................. 216
Normal Operation ............................................ 219
Start Condition ................................................. 201
Condition (Case 1) ........................................... 202
Condition (Case 2) ........................................... 202
Condition (SCL = 0) ......................................... 201
Condition (Case 1) ........................................... 203
Condition (Case 2) ........................................... 203
Condition (SDA Only) ...................................... 200
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