DSPIC33FJ128MC710-E/PT Microchip Technology, DSPIC33FJ128MC710-E/PT Datasheet - Page 26
![IC DSPIC MCU/DSP 128K 100TQFP](/photos/12/13/121330/c04-100-tqfp_sml.jpg)
DSPIC33FJ128MC710-E/PT
Manufacturer Part Number
DSPIC33FJ128MC710-E/PT
Description
IC DSPIC MCU/DSP 128K 100TQFP
Manufacturer
Microchip Technology
Series
dsPIC™ 33Fr
Datasheets
1.DSPIC33FJ12GP201-ISO.pdf
(90 pages)
2.DSPIC33FJ64MC506-IPT.pdf
(340 pages)
3.DSPIC33FJ64MC506-IPT.pdf
(30 pages)
Specifications of DSPIC33FJ128MC710-E/PT
Core Processor
dsPIC
Core Size
16-Bit
Speed
40 MIPs
Connectivity
CAN, I²C, IrDA, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, Motor Control PWM, QEI, POR, PWM, WDT
Number Of I /o
85
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 24x10b/12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
100-TFQFP
For Use With
AC164333 - MODULE SKT FOR PM3 100QFPMA330013 - MODULE PLUG-IN DSPIC33 100TQFPDV164033 - KIT START EXPLORER 16 MPLAB ICD2DM240001 - BOARD DEMO PIC24/DSPIC33/PIC32
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
- DSPIC33FJ12GP201-ISO PDF datasheet
- DSPIC33FJ64MC506-IPT PDF datasheet #2
- DSPIC33FJ64MC506-IPT PDF datasheet #3
- Current page: 26 of 340
- Download datasheet (5Mb)
dsPIC33FJXXXMCX06/X08/X10
3.3
The dsPIC33FJXXXMCX06/X08/X10 features a 17-bit
by 17-bit, single-cycle multiplier that is shared by both
the MCU ALU and DSP engine. The multiplier can per-
form signed, unsigned and mixed-sign multiplication.
Using a 17-bit by 17-bit multiplier for 16-bit by 16-bit
multiplication not only allows you to perform mixed-sign
multiplication, it also achieves accurate results for spe-
cial operations, such as (-1.0) x (-1.0).
FIGURE 3-1:
DS70287C-page 24
PSV and Table
Control Block
Data Access
Program Memory
Special MCU Features
Address Latch
Data Latch
23
23
Controller
Interrupt
dsPIC33FJXXXMCX06/X08/X10 CPU CORE BLOCK DIAGRAM
23
to Various Blocks
Control Signals
Decode and
Control
Stack
Logic
Instruction
PCU
Program Counter
Control
24
8
PCH
Control
Logic
Loop
16
PCL
Divide Support
DSP Engine
16
Y Data Bus
X Data Bus
Instruction Reg
Data Latch
ROM Latch
Address Generator Units
Address
X RAM
Latch
The dsPIC33FJXXXMCX06/X08/X10 supports 16/16
and 32/16 divide operations, both fractional and inte-
ger. All divide instructions are iterative operations. They
must be executed within a REPEAT loop, resulting in a
total execution time of 19 instruction cycles. The divide
operation can be interrupted during any of those
19 cycles without a loss of data.
A 40-bit barrel shifter is used to perform up to a 16-bit
left or right shift in a single cycle. The barrel shifter can
be used by both MCU and DSP instructions.
16
16
Data Latch
W Register Array
Address
Y RAM
Latch
EA MUX
16 x 16
16
16
16
16-bit ALU
16
16
© 2009 Microchip Technology Inc.
16
16
Controller
DMA
RAM
DMA
To Peripheral Modules
16
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