DSPIC33FJ128MC710-E/PT Microchip Technology, DSPIC33FJ128MC710-E/PT Datasheet - Page 52
![IC DSPIC MCU/DSP 128K 100TQFP](/photos/12/13/121330/c04-100-tqfp_sml.jpg)
DSPIC33FJ128MC710-E/PT
Manufacturer Part Number
DSPIC33FJ128MC710-E/PT
Description
IC DSPIC MCU/DSP 128K 100TQFP
Manufacturer
Microchip Technology
Series
dsPIC™ 33Fr
Datasheets
1.DSPIC33FJ12GP201-ISO.pdf
(90 pages)
2.DSPIC33FJ64MC506-IPT.pdf
(340 pages)
3.DSPIC33FJ64MC506-IPT.pdf
(30 pages)
Specifications of DSPIC33FJ128MC710-E/PT
Core Processor
dsPIC
Core Size
16-Bit
Speed
40 MIPs
Connectivity
CAN, I²C, IrDA, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, Motor Control PWM, QEI, POR, PWM, WDT
Number Of I /o
85
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
16K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 24x10b/12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
100-TFQFP
For Use With
AC164333 - MODULE SKT FOR PM3 100QFPMA330013 - MODULE PLUG-IN DSPIC33 100TQFPDV164033 - KIT START EXPLORER 16 MPLAB ICD2DM240001 - BOARD DEMO PIC24/DSPIC33/PIC32
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
- DSPIC33FJ12GP201-ISO PDF datasheet
- DSPIC33FJ64MC506-IPT PDF datasheet #2
- DSPIC33FJ64MC506-IPT PDF datasheet #3
- Current page: 52 of 340
- Download datasheet (5Mb)
TABLE 4-10:
TABLE 4-11:
TABLE 4-12:
I2C1RCV
I2C1TRN
I2C1BRG
I2C1CON
I2C1STAT
I2C1ADD
I2C1MSK
Legend:
I2C2RCV
I2C2TRN
I2C2BRG
I2C2CON
I2C2STAT
I2C2ADD
I2C2MSK
Legend:
QEI1CON
DFLT1CON 01E2
POS1CNT
MAX1CNT
Legend:
SFR Name
SFR Name
Name
SFR
u = uninitialized bit, — = unimplemented, read as ‘0’
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Addr
01E0 CNTERR
01E4
01E6
Addr
0200
0202
0204
0206
0208
020A
020C
Addr
021A
021C
SFR
SFR
0210
0212
0214
0216
0218
.
QEI REGISTER MAP
I2C1 REGISTER MAP
I2C2 REGISTER MAP
Bit 15
—
ACKSTAT
ACKSTAT
Bit 15
I2CEN
Bit 15
I2CEN
—
—
—
—
—
—
—
—
—
—
Bit 14
—
—
TRSTAT
TRSTAT
Bit 14
Bit 14
—
—
—
—
—
—
—
—
—
—
—
—
QEISIDL
Bit 13
—
I2CSIDL
I2CSIDL
Bit 13
Bit 13
—
—
—
—
—
—
—
—
—
—
—
—
Bit 12 Bit 11
INDX UPDN
—
SCLREL
SCLREL
Bit 12
Bit 12
—
—
—
—
—
—
—
—
—
—
—
—
—
Bit 10
IPMIEN
IMV<1:0>
IPMIEN
Bit 11
Bit 11
—
—
—
—
—
—
—
—
—
—
—
—
QEIM<2:0>
Bit 9
Bit 10
A10M
Bit 10
A10M
BCL
BCL
—
—
—
—
—
—
—
—
—
—
CEID
Bit 8
Maximum Count<15:0>
Position Counter<15:0>
GCSTAT
DISSLW
DISSLW
GCSTAT
Bit 9
SWPAB PCDOUT
QEOUT
Bit 9
—
—
—
Bit 7
—
—
—
ADD10
SMEN
ADD10
Bit 8
SMEN
Bit 8
—
—
Bit 6
—
—
IWCOL
QECK<2:0>
GCEN
IWCOL
GCEN
Bit 7
TQGATE
Bit 7
Bit 5
STREN
STREN
I2COV
I2COV
Bit 6
Bit 6
Bit 4
TQCKPS<1:0>
Address Mask Register
Address Mask Register
ACKDT
ACKDT
Baud Rate Generator Register
Baud Rate Generator Register
Bit 5
Address Register
Address Register
Bit 5
D_A
D_A
Bit 3
—
ACKEN
ACKEN
Transmit Register
Transmit Register
Receive Register
Bit 4
Receive Register
Bit 4
POSRES TQCS UPDN_SRC 0000 0000 0000 0000
P
P
Bit 2
—
RCEN
RCEN
Bit 3
Bit 3
S
S
Bit 1
—
Bit 2
R_W
Bit 2
R_W
PEN
PEN
Bit 0
—
RSEN
RSEN
Bit 1
Bit 1
RBF
RBF
0000 0000 0000 0000
0000 0000 0000 0000
1111 1111 1111 1111
Reset State
Bit 0
SEN
Bit 0
TBF
SEN
TBF
Resets
Resets
0000
00FF
0000
1000
0000
0000
0000
0000
00FF
0000
1000
0000
0000
0000
All
All
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