AT90CAN32-16MU Atmel, AT90CAN32-16MU Datasheet - Page 96

• Manufacturer Part Number: AT90CAN32-16MU
• Description: IC MCU AVR 32K FLASH 64-QFN
• Manufacturer: Atmel
• Series: AVR® 90CANr

Specifications of AT90CAN32-16MU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: CAN, EBI/EMI, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-VQFN Exposed Pad, 64-HVQFN, 64-SQFN, 64-DHVQFN
• Processor Series: AT90CANx
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: 2-Wire, SPI, USART
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 53
• Number Of Timers: 2
• Operating Supply Voltage: 0.5 V to 0.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATDVK90CAN1, ATADAPCAN01
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Cpu Family: 90C
• Device Core: AVR
• Device Core Size: 8b
• Frequency (max): 16MHz
• Total Internal Ram Size: 2KB
• # I/os (max): 53
• Number Of Timers - General Purpose: 4
• Operating Supply Voltage (typ): 3.3/5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 2.7V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 64
• Package Type: QFN EP
• Package: 64QFN EP
• Family Name: 90C
• Maximum Speed: 16 MHz
• For Use With: ATSTK600-TQFP64 - STK600 SOCKET/ADAPTER 64-TQFP770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAGATDVK90CAN1 - KIT DEV FOR AT90CAN128 MCU
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

11. Timer/Counter3/1/0 Prescalers
11.1
11.1.1
11.1.2
11.1.3
96
Overview
AT90CAN32/64/128
Internal Clock Source
Prescaler Reset
External Clock Source
Timer/Counter3, Timer/Counter1 and Timer/Counter0 share the same prescaler module, but the
Timer/Counters can have different prescaler settings. The description below applies to both
Timer/Counter3, Timer/Counter1 and Timer/Counter0.
Most bit references in this section are written in general form. A lower case “n” replaces the
Timer/Counter number.
The Timer/Counter can be clocked directly by the system clock (by setting the CSn2:0 = 1). This
provides the fastest operation, with a maximum Timer/Counter clock frequency equal to system
clock frequency (f
clock source. The prescaled clock has a frequency of either f
f
The prescaler is free running, i.e., operates independently of the Clock Select logic of the
Timer/Counter, and it is shared by Timer/Counter3, Timer/Counter1 and Timer/Counter0. Since
the prescaler is not affected by the Timer/Counter’s clock select, the state of the prescaler will
have implications for situations where a prescaled clock is used. One example of prescaling arti-
facts occurs when the timer is enabled and clocked by the prescaler (6 > CSn2:0 > 1). The
number of system clock cycles from when the timer is enabled to the first count occurs can be
from 1 to N+1 system clock cycles, where N equals the prescaler divisor (8, 64, 256, or 1024).
It is possible to use the prescaler reset for synchronizing the Timer/Counter to program execu-
tion. However, care must be taken if the other Timer/Counter that shares the same prescaler
also uses prescaling. A prescaler reset will affect the prescaler period for all Timer/Counters it is
connected to.
An external clock source applied to the T3/T1/T0 pin can be used as Timer/Counter clock
(clk
chronization logic. The synchronized (sampled) signal is then passed through the edge detector.
Figure 11-1
edge detector logic. The registers are clocked at the positive edge of the internal system clock
(
The edge detector generates one clk
tive (CSn2:0 = 6) edge it detects.
CLK_I/O
clk
I/O
T3
). The latch is transparent in the high period of the internal system clock.
/clk
/1024.
T1
/clk
shows a functional equivalent block diagram of the T3/T1/T0 synchronization and
T0
). The T3/T1/T0 pin is sampled once every system clock cycle by the pin syn-
CLK_I/O
). Alternatively, one of four taps from the prescaler can be used as a
T3
/clk
T1
/clk
T0
pulse for each positive (CSn2:0 = 7) or nega-
CLK_I/O
/8, f
CLK_I/O
/64, f
7679H–CAN–08/08
CLK_I/O
/256, or