PIC18F458T-I/PT Microchip Technology, PIC18F458T-I/PT Datasheet - Page 106

• Manufacturer Part Number: PIC18F458T-I/PT
• Description: IC MCU FLASH 16KX16 W/CAN 44TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F458T-I/PT

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: CAN, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 33
• Program Memory Size: 32KB (16K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-TQFP, 44-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

9.5
PORTE is a 3-bit wide, bidirectional port. PORTE has
three pins (RE0/AN5/RD, RE1/AN6/WR/C1OUT and
RE2/AN7/CS/C2OUT) which are individually config-
urable as inputs or outputs. These pins have Schmitt
Trigger input buffers.
Read-modify-write operations on the LATE register,
read and write the latched output value for PORTE.
The corresponding Data Direction register for the port
is TRISE. Setting a TRISE bit (= 1) will make the
corresponding PORTE pin an input (i.e., put the corre-
sponding output driver in a high-impedance mode).
Clearing a TRISE bit (= 0) will make the corresponding
PORTE pin an output (i.e., put the contents of the
output latch on the selected pin).
The TRISE register also controls the operation of the
Parallel Slave Port through the control bits in the upper
half of the register. These are shown in Register 9-1.
FIGURE 9-10:
DS41159E-page 104
PIC18FXX8
Note:
Note 1: I/O pins have diode protection to V
Peripheral Out Select
Peripheral Data Out
RD LATE
WR TRISE
RD TRISE
Peripheral Enable
RD PORTE
Peripheral Data In
Data Bus
WR LATE
or
WR PORTE
PORTE, TRISE and LATE
Registers
This port is only available on the
PIC18F448 and PIC18F458.
PORTE BLOCK DIAGRAM
TRIS Latch
Data
D
D
CK
CK
Latch
Q
Q
Q
Q
DD
Override
TRIS
and V
0
1
Q
SS
.
EN
D
When the Parallel Slave Port is active, the PORTE pins
function as its control inputs. For additional details,
refer to Section 10.0 “Parallel Slave Port”.
PORTE pins are also multiplexed with inputs for the A/D
converter and outputs for the analog comparators. When
selected as an analog input, these pins will read as ‘0’s.
Direction bits TRISE<2:0> control the direction of the RE
pins, even when they are being used as analog inputs.
The user must make sure to keep the pins configured as
inputs when using them as analog inputs.
EXAMPLE 9-5:
CLRF
CLRF
MOVLW
MOVWF
Schmitt
Trigger
V
V
P
N
SS
DD
PORTE
LATE
03h
TRISE
I/O pin
RE0
RE1
RE2
Pin
INITIALIZING PORTE
; Initialize PORTE by
; clearing output
; data latches
; Alternate method
; to clear output
; data latches
; Value used to
; initialize data
; direction
; Set RE1:RE0 as inputs
; RE2 as an output
; (RE4=0 - PSPMODE Off)
© 2006 Microchip Technology Inc.
(1)
TRIS OVERRIDE
Override Peripheral
Yes
Yes
Yes
PSP
PSP
PSP