PIC18F458T-I/PT Microchip Technology, PIC18F458T-I/PT Datasheet - Page 138

• Manufacturer Part Number: PIC18F458T-I/PT
• Description: IC MCU FLASH 16KX16 W/CAN 44TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F458T-I/PT

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: CAN, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 33
• Program Memory Size: 32KB (16K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-TQFP, 44-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

16.5.2
In the Half-Bridge Output mode, two pins are used as
outputs to drive push-pull loads. The RD4/PSP4/
ECCP1/P1A pin has the PWM output signal, while the
RD5/PSP5/P1B pin has the complementary PWM
output signal (Figure 16-3). This mode can be used for
half-bridge applications, as shown in Figure 16-4, or for
full-bridge applications where four power switches are
being modulated with two PWM signals.
In Half-Bridge Output mode, the programmable dead-
band delay can be used to prevent shoot-through
current in bridge power devices. The value of register
ECCP1DEL dictates the number of clock cycles before
the output is driven active. If the value is greater than
the duty cycle, the corresponding output remains
inactive during the entire cycle. See Section 16.5.4
“Programmable Dead-Band Delay” for more details
of the dead-band delay operations.
Since the P1A and P1B outputs are multiplexed with
the PORTD<4> and PORTD<5> data latches, the
TRISD<4> and TRISD<5> bits must be cleared to
configure P1A and P1B as outputs.
FIGURE 16-4:
DS41159E-page 136
PIC18FXX8
Standard Half-Bridge Circuit (“Push-Pull”)
Half-Bridge Output Driving a Full-Bridge Circuit
HALF-BRIDGE MODE
PIC18F448/458
EXAMPLES OF HALF-BRIDGE OUTPUT MODE APPLICATIONS
P1A
P1B
PIC18F448/458
P1A
P1B
FET
Driver
FET
Driver
FET
Driver
FET
Driver
FIGURE 16-3:
+
P1A
P1B
td = Dead-Band Delay
Load
Note 1: At this time, the TMR2 register is equal to the
V+
V-
(2)
(2)
V+
V-
(1)
2: Output signals are shown as asserted high.
-
+
td
Duty Cycle
PR2 register.
Load
Period
-
td
FET
Driver
FET
Driver
HALF-BRIDGE PWM
OUTPUT
© 2006 Microchip Technology Inc.
+
V
-
+
V
-
(1)
Period
(1)