PIC18F458T-I/PT Microchip Technology, PIC18F458T-I/PT Datasheet - Page 123

• Manufacturer Part Number: PIC18F458T-I/PT
• Description: IC MCU FLASH 16KX16 W/CAN 44TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F458T-I/PT

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: CAN, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 33
• Program Memory Size: 32KB (16K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-TQFP, 44-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

14.2
The Timer1 oscillator may be used as the clock source
for Timer3. The Timer1 oscillator is enabled by setting
the T1OSCEN bit (T1CON register). The oscillator is a
low-power oscillator rated up to 50 kHz. Refer to
Section 12.0 “Timer1 Module” for Timer1 oscillator
details.
14.3
The TMR3 register pair (TMR3H:TMR3L) increments
from 0000h to 0FFFFh and rolls over to 0000h. The
TMR3 interrupt, if enabled, is generated on overflow
which is latched in interrupt flag bit TMR3IF (PIR regis-
ters). This interrupt can be enabled/disabled by setting/
clearing TMR3 Interrupt Enable bit, TMR3IE (PIE
registers).
TABLE 14-1:
© 2006 Microchip Technology Inc.
INTCON
PIR2
PIE2
IPR2
TMR3L
TMR3H
T1CON
T3CON
Legend:
Name
Timer1 Oscillator
Timer3 Interrupt
Holding Register for the Least Significant Byte of the 16-bit TMR3 Register
Holding Register for the Most Significant Byte of the 16-bit TMR3 Register
GIE/ GIEH PEIE/GIEL
x = unknown, u = unchanged, - = unimplemented, read as ‘0’. Shaded cells are not used by the Timer1 module.
RD16
RD16
Bit 7
—
—
—
REGISTERS ASSOCIATED WITH TIMER3 AS A TIMER/COUNTER
T3ECCP1 T3CKPS1 T3CKPS0
CMIF
CMIE
CMIP
Bit 6
—
T1CKPS1 T1CKPS0 T1OSCEN T1SYNC TMR1CS TMR1ON 0-00 0000 u-uu uuuu
TMR0IE
Bit 5
—
—
—
INT0IE
Bit 4
EEIF
EEIE
EEIP
T3CCP1
BCLIF
BCLIE
BCLIP
RBIE
Bit 3
14.4
If the CCP module is configured in Compare mode
to
(CCP1M3:CCP1M0 = 1011), this signal will reset
Timer3.
Timer3 must be configured for either Timer or Synchro-
nized Counter mode to take advantage of this feature. If
Timer3 is running in Asynchronous Counter mode, this
Reset operation may not work. In the event that a write
to Timer3 coincides with a special event trigger from
CCP1, the write will take precedence. In this mode of
operation, the CCPR1H:CCPR1L register pair becomes
the period register for Timer3. Refer to Section 15.0
“Capture/Compare/PWM (CCP) Modules” for CCP
details.
T3SYNC TMR3CS TMR3ON 0000 0000 uuuu uuuu
TMR0IF
Note:
LVDIF
LVDIE
LVDIP
Bit 2
generate
Resetting Timer3 Using a CCP
Trigger Output
The special event triggers from the CCP
module will not set interrupt flag bit
TMR3IF (PIR registers).
TMR3IE ECCP1IE -0-0 0000 -0-0 0000
TMR3IP ECCP1IP -1-1 1111 -1-1 1111
TMR3IF ECCP1IF -0-0 0000 -0-0 0000
INT0IF
Bit 1
a
RBIF
Bit 0
PIC18FXX8
“special
0000 000x 0000 000u
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
POR, BOR
Value on
DS41159E-page 121
event
Value on
all other
Resets
trigger”