AT32UC3B0512-Z2UR Atmel, AT32UC3B0512-Z2UR Datasheet - Page 100

• Manufacturer Part Number: AT32UC3B0512-Z2UR
• Description: IC MCU AVR32 512K FLASH 64QFN
• Manufacturer: Atmel
• Series: AVR®32 UC3r

Specifications of AT32UC3B0512-Z2UR

• Package / Case: 64-QFN
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Operating Temperature: -40°C ~ 85°C
• Speed: 60MHz
• Number Of I /o: 44
• Core Processor: AVR
• Program Memory Type: FLASH
• Ram Size: 96K x 8
• Program Memory Size: 512KB (512K x 8)
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Connectivity: I²C, IrDA, SPI, SSC, UART/USART, USB
• Core Size: 32-Bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

13.5.2
13.5.3
13.5.4
13.5.5
13.6
13.6.1
32059J–12/2010
Functional Description
Power Management
Clocks
Interrupts
Debug Operation
External Interrupts
All interrupts are available in all sleep modes as long as the EIC module is powered. However, in
sleep modes where CLK_SYNC is stopped, the interrupt must be configured to asynchronous
mode.
The clock for the EIC bus interface (CLK_EIC) is generated by the Power Manager. This clock is
enabled at reset, and can be disabled in the Power Manager.
The filter and synchronous edge/level detector runs on a clock which is stopped in any of the
sleep modes where the system RC oscillator is not running. This clock is referred to as
CLK_SYNC. Refer to the Module Configuration section at the end of this chapter for details.
The Keypad scan function operates on the system RC oscillator clock CLK_RCSYS.
The external interrupt request lines are connected to the interrupt controller. Using the external
interrupts requires the interrupt controller to be programmed first.
Using the Non-Maskable Interrupt does not require the interrupt controller to be programmed.
The EIC is frozen during debug operation, unless the OCD system keeps peripherals running
during debug operation.
The external interrupts are not enabled by default, allowing the proper interrupt vectors to be set
up by the CPU before the interrupts are enabled.
Each external interrupt INTn can be configured to produce an interrupt on rising or falling edge,
or high or low level. External interrupts are configured by the MODE, EDGE, and LEVEL regis-
ters. Each interrupt n has a bit INTn in each of these registers. Writing a zero to the INTn bit in
the MODE register enables edge triggered interrupts, while writing a one to the bit enables level
triggered interrupts.
If INTn is configured as an edge triggered interrupt, writing a zero to the INTn bit in the EDGE
register will cause the interrupt to be triggered on a falling edge on EXTINTn, while writing a one
to the bit will cause the interrupt to be triggered on a rising edge on EXTINTn.
If INTn is configured as a level triggered interrupt, writing a zero to the INTn bit in the LEVEL
register will cause the interrupt to be triggered on a low level on EXTINTn, while writing a one to
the bit will cause the interrupt to be triggered on a high level on EXTINTn.
Each interrupt has a corresponding bit in each of the interrupt control and status registers. Writ-
ing a one to the INTn bit in the Interrupt Enable Register (IER) enables the external interrupt
from pin EXTINTn to propagate from the EIC to the interrupt controller, while writing a one to
INTn bit in the Interrupt Disable Register (IDR) disables this propagation. The Interrupt Mask
Register (IMR) can be read to check which interrupts are enabled. When an interrupt triggers,
the corresponding bit in the Interrupt Status Register (ISR) will be set. This bit remains set until a
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