AT32UC3B0512-Z2UR Atmel, AT32UC3B0512-Z2UR Datasheet - Page 609

• Manufacturer Part Number: AT32UC3B0512-Z2UR
• Description: IC MCU AVR32 512K FLASH 64QFN
• Manufacturer: Atmel
• Series: AVR®32 UC3r

Specifications of AT32UC3B0512-Z2UR

• Package / Case: 64-QFN
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Operating Temperature: -40°C ~ 85°C
• Speed: 60MHz
• Number Of I /o: 44
• Core Processor: AVR
• Program Memory Type: FLASH
• Ram Size: 96K x 8
• Program Memory Size: 512KB (512K x 8)
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Connectivity: I²C, IrDA, SPI, SSC, UART/USART, USB
• Core Size: 32-Bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

27.5.3.3
32059J–12/2010
MEMORY_SIZED_ACCESS
6. In Shift-DR: Scan in the direction bit (1=read, 0=write) and the 7-bit address for the Mem-
7. Go to Update-DR and re-enter Select-DR Scan.
8. In Shift-DR: For a read operation, scan out the contents of the addressed register. For a
9. Return to Run-Test/Idle.
For any operation, the full 7 bits of the address must be provided. For write operations, 32 data
bits must be provided, or the result will be undefined. For read operations, shifting may be termi-
nated once the required number of bits have been acquired.
Table 27-17. MEMORY_SERVICE Details
This instruction allows access to the entire Service Access Bus data area. Data is accessed
through a 36-bit byte index, a 2-bit size, a direction bit, and 8, 16, or 32 bits of data. Not all units
mapped on the SAB bus may support all sizes of accesses, e.g., some may only support word
accesses.
The data register is alternately interpreted by the SAB as an address register and a data regis-
ter. The SAB starts in address mode after the MEMORY_SIZED_ACCESS instruction is
selected, and toggles between address and data mode each time a data scan completes with
the busy bit cleared.
Instructions
IR input value
IR output value
DR Size
DR input value (Address phase)
DR input value (Data read phase)
DR input value (Data write phase)
DR output value (Address phase)
DR output value (Data read phase)
DR output value (Data write phase)
ory Service register.
write operation, scan in the new contents of the register.
Details
10100 (0x14)
peb01
34 bits
aaaaaaar xxxxxxxx xxxxxxxx xxxxxxxx xx
xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx xx
dddddddd dddddddd dddddddd dddddddd xx
xx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxeb
eb dddddddd dddddddd dddddddd dddddddd
xx xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxeb
AT32UC3B
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