AT32UC3B0512-Z2UR Atmel, AT32UC3B0512-Z2UR Datasheet - Page 275

• Manufacturer Part Number: AT32UC3B0512-Z2UR
• Description: IC MCU AVR32 512K FLASH 64QFN
• Manufacturer: Atmel
• Series: AVR®32 UC3r

Specifications of AT32UC3B0512-Z2UR

• Package / Case: 64-QFN
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Operating Temperature: -40°C ~ 85°C
• Speed: 60MHz
• Number Of I /o: 44
• Core Processor: AVR
• Program Memory Type: FLASH
• Ram Size: 96K x 8
• Program Memory Size: 512KB (512K x 8)
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Connectivity: I²C, IrDA, SPI, SSC, UART/USART, USB
• Core Size: 32-Bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

20.7.8
20.7.9
32059J–12/2010
Loop Mode
Interrupt
Figure 20-15. Receive Frame Format in Continuous Mode
Note:
The receiver can be programmed to receive transmissions from the transmitter. This is done by
writing a one to the Loop Mode bit in RFMR register (RFMR.LOOP). In this case, RX_DATA is
connected to TX_DATA, RX_FRAME_SYNC is connected to TX_FRAME_SYNC and
RX_CLOCK is connected to TX_CLOCK.
Most bits in the SR register have a corresponding bit in interrupt management registers.
The SSC can be programmed to generate an interrupt when it detects an event. The interrupt is
controlled by writing to the Interrupt Enable Register (IER) and Interrupt Disable Register (IDR).
These registers enable and disable, respectively, the corresponding interrupt by setting and
clearing the corresponding bit in the Interrupt Mask Register (IMR), which controls the genera-
tion of interrupts by asserting the SSC interrupt line connected to the interrupt controller.
Figure 20-16. Interrupt Block Diagram
STTDLY is written to zero.
T ra n s m itte r
R e c e iv e r
T X E M P T Y
R X S Y N C
T X S Y N C
O V R U N
T X R D Y
R X R D Y
RX_DATA
Start = Enable Receiver
DATLEN
To RHR
Data
IE R
S e t
In te rru p t
C o n tro l
IM R
DATLEN
To RHR
Data
C le a r
ID R
S S C In te rru p t
AT32UC3B
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