DSPIC30F5015-30I/PT Microchip Technology, DSPIC30F5015-30I/PT Datasheet - Page 142

• Manufacturer Part Number: DSPIC30F5015-30I/PT
• Description: IC DSPIC MCU/DSP 66K 64TQFP
• Manufacturer: Microchip Technology
• Series: dsPIC™ 30Fr

Specifications of DSPIC30F5015-30I/PT

• Program Memory Type: FLASH
• Program Memory Size: 66KB (22K x 24)
• Package / Case: 64-TFQFP
• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 30 MIPs
• Connectivity: CAN, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, Motor Control PWM, QEI, POR, PWM, WDT
• Number Of I /o: 52
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Product: DSCs
• Data Bus Width: 16 bit
• Processor Series: DSPIC30F
• Core: dsPIC
• Maximum Clock Frequency: 30 MHz
• Number Of Programmable I/os: 52
• Data Ram Size: 2 KB
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52713-733, 52714-737, 53276-922, EWDSPIC
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE4000, DM240002, DM330011
• Minimum Operating Temperature: - 40 C
• Package: 64TQFP
• Device Core: dsPIC
• Family Name: dsPIC30
• Maximum Speed: 30 MHz
• Operating Supply Voltage: 3.3|5 V
• Interface Type: CAN/I2C/SPI/UART
• On-chip Adc: 16-chx10-bit
• Number Of Timers: 5
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT64PT5 - SOCKET TRAN ICE 64MQFP/TQFPAC164319 - MODULE SKT MPLAB PM3 64TQFPAC30F008 - MODULE SKT FOR DSPIC30F 64TQFPDV164005 - KIT ICD2 SIMPLE SUIT W/USB CABLE
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: DSPIC30F501530IPT

dsPIC30F5015/5016
20.4
The conversion trigger will terminate acquisition and
start the requested conversions.
The SSRC<2:0> bits select the source of the
conversion trigger.
The SSRC bits provide for up to five alternate sources
of conversion trigger.
When SSRC<2:0> = 000, the conversion trigger is
under software control. Clearing the SAMP bit will
cause the conversion trigger.
When SSRC<2:0> = 111 (Auto-Start mode), the con-
version trigger is under A/D clock control. The SAMC
bits select the number of A/D clocks between the start
of acquisition and the start of conversion. This provides
the fastest conversion rates on multiple channels.
SAMC must always be at least one clock cycle.
Other trigger sources can come from timer modules,
Motor Control PWM module, or external interrupts.
20.5
Clearing the ADON bit during a conversion will abort
the current conversion and stop the sampling sequenc-
ing. The ADCBUF will not be updated with the partially
completed A/D conversion sample. That is, the
ADCBUF will continue to contain the value of the last
completed conversion (or the last value written to the
ADCBUF register).
If the clearing of the ADON bit coincides with an
auto-start, the clearing has a higher priority.
After the A/D conversion is aborted, a 2 T
required before the next sampling may be started by
setting the SAMP bit.
If sequential sampling is specified, the A/D will continue
at the next sample pulse which corresponds with the next
channel converted. If simultaneous sampling is specified,
the A/D will continue with the next multichannel group
conversion sequence.
DS70149E-page 142
Note:
Programming the Start of
Conversion Trigger
Aborting a Conversion
To operate the ADC at the maximum
specified conversion speed, the Auto-
Convert Trigger option should be selected
(SSRC = 111) and the Auto-Sample Time
bits
(SAMC = 00001). This configuration will
give a total conversion period (sample +
convert) of 13 T
The use of any other conversion trigger will
result
synchronize the external event to the ADC.
should
in
additional
AD
be
.
set
T
AD
to
cycles
AD
1
wait is
T
AD
to
20.6
The A/D conversion requires 12 T
A/D conversion clock is software selected using a 6-bit
counter. There are 64 possible options for T
EQUATION 20-1:
The internal RC oscillator is selected by setting the
ADRC bit.
For correct A/D conversions, the A/D conversion clock
(T
of 83.33 nsec (for V
“Electrical Characteristics”
other operating conditions.
Example 20-1
ADCS<5:0> bits, assuming a device operating speed
of 30 MIPS.
EXAMPLE 20-1:
20.7
The dsPIC30F 10-bit ADC specifications permit a
maximum
summarizes the conversion speeds for the dsPIC30F
10-bit ADC and the required operating conditions.
AD
) must be selected to ensure a minimum T
Therefore,
Set ADCS<5:0> = 5
Selecting the A/D Conversion
Clock
ADC Speeds
ADCS<5:0> = 2
T
Actual T
AD
1
= T
ADCS<5:0> = 2
shows a sample calculation for the
Msps
CY
AD
T
T
* (0.5*(ADCS<5:0> +1))
AD
CY
DD
= 2 •
= 4.09
=
=
= 99 nsec
A/D CONVERSION CLOCK
A/D CONVERSION CLOCK
CALCULATION
= 84 nsec
= 33 nsec (30 MIPS)
© 2011 Microchip Technology Inc.
= 5V). Refer to
sampling
T
33 nsec
T
T
CY
2
AD
CY
84 nsec
2
33 nsec
for minimum T
(ADCS<5:0> + 1)
T
T
– 1
AD
CY
AD
(9 + 1)
. The source of the
rate.
– 1
– 1
Section 24.0
AD
Table 20-1
AD
.
AD
under
time