DSPIC30F5015-30I/PT Microchip Technology, DSPIC30F5015-30I/PT Datasheet - Page 20

• Manufacturer Part Number: DSPIC30F5015-30I/PT
• Description: IC DSPIC MCU/DSP 66K 64TQFP
• Manufacturer: Microchip Technology
• Series: dsPIC™ 30Fr

Specifications of DSPIC30F5015-30I/PT

• Program Memory Type: FLASH
• Program Memory Size: 66KB (22K x 24)
• Package / Case: 64-TFQFP
• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 30 MIPs
• Connectivity: CAN, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, Motor Control PWM, QEI, POR, PWM, WDT
• Number Of I /o: 52
• Eeprom Size: 1K x 8
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Product: DSCs
• Data Bus Width: 16 bit
• Processor Series: DSPIC30F
• Core: dsPIC
• Maximum Clock Frequency: 30 MHz
• Number Of Programmable I/os: 52
• Data Ram Size: 2 KB
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52713-733, 52714-737, 53276-922, EWDSPIC
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE4000, DM240002, DM330011
• Minimum Operating Temperature: - 40 C
• Package: 64TQFP
• Device Core: dsPIC
• Family Name: dsPIC30
• Maximum Speed: 30 MHz
• Operating Supply Voltage: 3.3|5 V
• Interface Type: CAN/I2C/SPI/UART
• On-chip Adc: 16-chx10-bit
• Number Of Timers: 5
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT64PT5 - SOCKET TRAN ICE 64MQFP/TQFPAC164319 - MODULE SKT MPLAB PM3 64TQFPAC30F008 - MODULE SKT FOR DSPIC30F 64TQFPDV164005 - KIT ICD2 SIMPLE SUIT W/USB CABLE
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: DSPIC30F501530IPT

dsPIC30F5015/5016
2.3
The dsPIC DSC devices feature a 16/16-bit signed
fractional divide operation, as well as 32/16-bit and
16/16-bit
operations, in the form of single instruction iterative
divides. The following instructions and data sizes are
supported:
• DIVF – 16/16 signed fractional divide
• DIV.sd – 32/16 signed divide
• DIV.ud – 32/16 unsigned divide
• DIV.sw – 16/16 signed divide
• DIV.uw – 16/16 unsigned divide
TABLE 2-1:
2.4
The DSP engine consists of a high-speed 17-bit x 17-bit
multiplier, a barrel shifter, and a 40-bit adder/subtracter
(with two target accumulators, round and saturation
logic).
The dsPIC30F devices have a single instruction flow
which can execute either DSP or MCU instructions.
Many of the hardware resources are shared between
the DSP and MCU instructions. For example, the
instruction set has both DSP and MCU multiply
instructions which use the same hardware multiplier.
The DSP engine also has the capability to perform inher-
ent
require no additional data. These instructions are ADD,
SUB and NEG.
The DSP engine has various options selected through
various bits in the CPU Core Configuration register
(CORCON), as listed below:
• Fractional or Integer DSP Multiply (IF).
• Signed or Unsigned DSP Multiply (US).
• Conventional or Convergent Rounding (RND).
• Automatic Saturation On/Off for ACCA (SATA).
• Automatic Saturation On/Off for ACCB (SATB).
• Automatic Saturation On/Off for Writes to Data
• Accumulator Saturation mode Selection
DS70149E-page 20
DIVF
DIV.sd
DIV.ud
DIV.sw
DIV.uw
Memory (SATDW).
(ACCSAT).
Note:
accumulator-to-accumulator
Divide Support
DSP Engine
signed
For CORCON layout, see
Instruction
DIVIDE INSTRUCTIONS
and
unsigned
operations,
Table
integer
Signed fractional divide: Wm/Wn → W0; Rem → W1
Signed divide: (Wm+1:Wm)/Wn → W0; Rem → W1
Unsigned divide: (Wm+1:Wm)/Wn → W0; Rem → W1
Signed divide: Wm/Wn → W0; Rem → W1
Unsigned divide: Wm/Wn → W0; Rem → W1
3-3.
divide
which
The divide instructions must be executed within a
REPEAT loop. Any other form of execution (e.g. a series
of discrete divide instructions) will not function correctly
because the instruction flow depends on RCOUNT. The
divide instruction does not automatically set up the
RCOUNT value, and it must, therefore, be explicitly and
correctly specified in the REPEAT instruction, as shown
in
{operand value+1} times). The REPEAT loop count must
be set up for 18 iterations of the DIV/DIVF instruction.
Thus, a complete divide operation requires 19 cycles.
A block diagram of the DSP engine is shown in
Figure
TABLE 2-2:
CLR
ED
EDAC
MAC
MOVSAC
MPY
MPY.N
MSC
Note:
Table 2-1
Instruction
2-2.
Function
The divide flow is interruptible. However,
the user needs to save the context as
appropriate.
(REPEAT will execute the target instruction
DSP INSTRUCTION
SUMMARY
© 2011 Microchip Technology Inc.
Algebraic Operation
A = 0
A = (x – y)
A = A + (x – y)
A = A + (x * y)
No change in A
A = x * y
A = – x * y
A = A – x * y
2
2