AT32UC3A1512-AUR Atmel, AT32UC3A1512-AUR Datasheet - Page 573

• Manufacturer Part Number: AT32UC3A1512-AUR
• Description: MCU 32BIT 512KB FLASH 100-TQFP
• Manufacturer: Atmel
• Series: AVR®32 UC3r

Specifications of AT32UC3A1512-AUR

• Core Processor: AVR
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: Ethernet, I²C, SPI, SSC, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 69
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP, 100-VQFP
• For Use With: ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMR770-1008 - ISP 4PORT ATMEL AVR32 MCU SPIATSTK600-TQFP100 - STK600 SOCKET/ADAPTER 100-TQFPATEVK1100 - KIT DEV/EVAL FOR AVR32 AT32UC3A
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

30.8.2.11
Offset:
Register Name:
Access Type:
Reset Value:
• TXINI: Transmitted IN Data Interrupt Flag
For control endpoints:
For isochronous, bulk and interrupt IN endpoints:
This bit is inactive (cleared) for isochronous, bulk and interrupt OUT endpoints.
• RXOUTI: Received OUT Data Interrupt Flag
For control endpoints:
32058J–AVR32–04/11
PACKET
SHORT
Set by hardware when the current bank is ready to accept a new IN packet. This triggers an EPXINT interrupt if
TXINE = 1.
Shall be cleared by software (by setting the TXINIC bit) to acknowledge the interrupt and to send the packet.
Set by hardware at the same time as FIFOCON when the current bank is free. This triggers an EPXINT interrupt if
TXINE = 1.
Shall be cleared by software (by setting the TXINIC bit) to acknowledge the interrupt, what has no effect on the end-
point FIFO.
The software then writes into the FIFO and clears the FIFOCON bit to allow the USB controller to send the data. If
the IN endpoint is composed of multiple banks, this also switches to the next bank. The TXINI and FIFOCON bits are
updated by hardware in accordance with the status of the next bank.
TXINI shall always be cleared before clearing FIFOCON.
Set by hardware when the current bank contains a bulk OUT packet (data or status stage). This triggers an EPXINT
interrupt if RXOUTE = 1.
31
23
15
ru
–
0
0
7
0
CURRBK
USB Endpoint X Status Register (UESTAX)
ru
STALLEDI/
CRCERRI
30
22
14
ru
0
0
0
6
0
BYCT
ru
OVERFI
29
21
13
ru
0
0
0
5
0
0x0130 + X . 0x04
UESTAX, X in [0..6]
Read-Only
0x00000100
NBUSYBK
ru
NAKINI
28
20
12
ru
0
0
0
4
0
NAKOUTI
BYCT
27
19
11
ru
ru
0
–
–
3
0
UNDERFI
RXSTPI/
CFGOK
26
18
10
ru
ru
0
0
–
2
0
CTRLDIR
RXOUTI
25
17
ru
ru
0
0
9
0
1
0
AT32UC3A
DTSEQ
ru
RWALL
TXINI
24
16
ru
ru
0
0
8
1
0
0
573