AT32UC3A1512-AUR Atmel, AT32UC3A1512-AUR Datasheet - Page 696

• Manufacturer Part Number: AT32UC3A1512-AUR
• Description: MCU 32BIT 512KB FLASH 100-TQFP
• Manufacturer: Atmel
• Series: AVR®32 UC3r

Specifications of AT32UC3A1512-AUR

• Core Processor: AVR
• Core Size: 32-Bit
• Speed: 66MHz
• Connectivity: Ethernet, I²C, SPI, SSC, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 69
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-TQFP, 100-VQFP
• For Use With: ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMR770-1008 - ISP 4PORT ATMEL AVR32 MCU SPIATSTK600-TQFP100 - STK600 SOCKET/ADAPTER 100-TQFPATEVK1100 - KIT DEV/EVAL FOR AVR32 AT32UC3A
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

32.7.12
Register Name:
Access Type:
Only the first 20 bits (internal channel counter size) are significant.
•
If the waveform is left-aligned, then the output waveform period depends on the counter source clock and can be
calculated:
If the waveform is center-aligned, then the output waveform period depends on the counter source clock and can be
calculated:
32058J–AVR32–04/11
CPRD: Channel Period
31
23
15
7
PWM Channel Period Register
30
22
14
6
– By using the Master Clock (MCK) divided by an X given prescaler value (with X being
– By using a Master Clock divided by one of both DIVA or DIVB divider, the formula
– By using the Master Clock (MCK) divided by an X given prescaler value (with X being
– By using a Master Clock divided by one of both DIVA or DIVB divider, the formula
1, 2, 4, 8, 16, 32, 64, 128, 256, 512, or 1024). The resulting period formula will be:
becomes, respectively:
1, 2, 4, 8, 16, 32, 64, 128, 256, 512, or 1024). The resulting period formula will be:
becomes, respectively:
(
------------------------------ -
(
----------------------------------------- -
(
---------------------------------------- - -
(
--------------------------------------------------- - -
X CPRD
CRPD
2
2
×
×
×
MCK
X CPRD
CPRD DIVA
29
21
13
MCK
5
MCK
CPRDx
Read/Write
×
MCK
×
DIVA
)
×
)
)
or
)
(
--------------------------------------------- -
or
CRPD
28
20
12
4
(
--------------------------------------------------- - -
2 CPRD
MCK
×
CPRD
CPRD
CPRD
CPRD
×
DIVAB
MCK
×
)
DIVB
27
19
11
3
)
26
18
10
2
25
17
9
1
AT32UC3A
24
16
8
0
696