AT32UC3B1256-AUT Atmel, AT32UC3B1256-AUT Datasheet - Page 225

• Manufacturer Part Number: AT32UC3B1256-AUT
• Description: IC MCU AVR32 256KB FLASH 48-TQFP
• Manufacturer: Atmel
• Series: AVR®32 UC3r

Specifications of AT32UC3B1256-AUT

• Core Processor: AVR
• Core Size: 32-Bit
• Speed: 60MHz
• Connectivity: I²C, IrDA, SPI, SSC, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 28
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 6x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-TQFP, 48-VQFP
• Processor Series: AT32UC3x
• Core: AVR32
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: 2-Wire/SPI/USART
• Maximum Clock Frequency: 60 MHz
• Number Of Programmable I/os: 28
• Number Of Timers: 3
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR32, EWAVR32-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATEXTWIFI, ATEVK1101
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 6-ch x 10-bit
• Controller Family/series: AVR UC3
• No. Of I/o's: 28
• Ram Memory Size: 32KB
• Cpu Speed: 60MHz
• No. Of Timers: 1
• Rohs Compliant: Yes
• For Use With: ATSTK600-TQFP48 - STK600 SOCKET/ADAPTER 48-TQFPATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMR770-1008 - ISP 4PORT ATMEL AVR32 MCU SPIATEVK1101 - KIT DEV/EVAL FOR AVR32 AT32UC3B
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

19.10.7.1
Figure 19-11. Master Write with One, Two or Three Bytes Internal Address and One Data Byte
32059K–03/2011
TWD
TWD
TWD
Three bytes internal address
Two bytes internal address
One byte internal address
S
S
S
7-bit Slave Addressing
DADR
DADR
DADR
When Addressing 7-bit slave devices, the internal address bytes are used to perform random
address (read or write) accesses to reach one or more data bytes, within a memory page loca-
tion in a serial memory, for example. When performing read operations with an internal address,
the TWI performs a write operation to set the internal address into the slave device, and then
switch to Master Receiver mode. Note that the second start condition (after sending the IADR) is
sometimes called “repeated start” (Sr) in I2C fully-compatible devices. See
Figure 19-11
The three internal address bytes are configurable through the Master Mode register (MMR).
If the slave device supports only a 7-bit address, i.e. no internal address, IADRSZ must be set to
0.
n the figures below the following abbreviations are used:I
• S
• Sr
• P
• W
• R
• A
• N
• DADR
• IADR
W
W
W
A
A
A
and
IADR(23:16)
IADR(15:8)
IADR(7:0)
Start
Repeated Start
Stop
Write
Read
Acknowledge
Not Acknowledge
Device Address
Internal Address
Figure 19-13
A
A
A
for Master Write operation with internal address.
IADR(15:8)
IADR(7:0)
DATA
A
A
A
IADR(7:0)
P
DATA
A
A
P
DATA
AT32UC3B
Figure
A
19-12. See
P
225