AT32UC3B1256-AUT Atmel, AT32UC3B1256-AUT Datasheet - Page 583
AT32UC3B1256-AUT
Manufacturer Part Number
AT32UC3B1256-AUT
Description
IC MCU AVR32 256KB FLASH 48-TQFP
Manufacturer
Atmel
Series
AVR®32 UC3r
Specifications of AT32UC3B1256-AUT
Core Processor
AVR
Core Size
32-Bit
Speed
60MHz
Connectivity
I²C, IrDA, SPI, SSC, UART/USART, USB
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
28
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Data Converters
A/D 6x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
48-TQFP, 48-VQFP
Processor Series
AT32UC3x
Core
AVR32
Data Bus Width
32 bit
Data Ram Size
32 KB
Interface Type
2-Wire/SPI/USART
Maximum Clock Frequency
60 MHz
Number Of Programmable I/os
28
Number Of Timers
3
Operating Supply Voltage
3.3 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR32, EWAVR32-BL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATEXTWIFI, ATEVK1101
Minimum Operating Temperature
- 40 C
On-chip Adc
6-ch x 10-bit
Controller Family/series
AVR UC3
No. Of I/o's
28
Ram Memory Size
32KB
Cpu Speed
60MHz
No. Of Timers
1
Rohs Compliant
Yes
For Use With
ATSTK600-TQFP48 - STK600 SOCKET/ADAPTER 48-TQFPATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMR770-1008 - ISP 4PORT ATMEL AVR32 MCU SPIATEVK1101 - KIT DEV/EVAL FOR AVR32 AT32UC3B
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AT32UC3B1256-AUT
Manufacturer:
ATMEL
Quantity:
1 000
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27. Programming and Debugging
27.1
27.2
27.2.1
27.2.2
32059K–03/2011
Overview
Service Access Bus
SAB address map
SAB security restrictions
General description of programming and debug features, block diagram and introduction of main
concepts.
The AVR32 architecture offers a common interface for access to On-Chip Debug, programming,
and test functions. These are mapped on a common bus called the Service Access Bus (SAB),
which is linked to the JTAG port through a bus master module, which also handles synchroniza-
tion between the debugger and SAB clocks.
When accessing the SAB through the debugger there are no limitations on debugger frequency
compared to chip frequency, although there must be an active system clock in order for the SAB
accesses to complete. If the system clock is switched off in sleep mode, activity on the debugger
will restart the system clock automatically, without waking the device from sleep. Debuggers
may optimize the transfer rate by adjusting the frequency in relation to the system clock. This
ratio can be measured with debug protocol specific instructions.
The Service Access Bus uses 36 address bits to address memory or registers in any of the
slaves on the bus. The bus supports sized accesses of bytes (8 bits), halfwords (16 bits), or
words (32 bits). All accesses must be aligned to the size of the access, i.e. halfword accesses
must have the lowest address bit cleared, and word accesses must have the two lowest address
bits cleared.
The Service Access Bus (SAB) gives the user access to the internal address space and other
features through a 36 bits address space. The 4 MSBs identify the slave number, while the 32
LSBs are decoded within the slave’s address space. The SAB slaves are shown in
on page
Table 27-1.
The Service Access bus can be restricted by internal security measures. A short description of
the security measures are found in the table below.
Memory Service
Unallocated
Reserved
Slave
OCD
HSB
HSB
Unit
583.
SAB Slaves, addresses and descriptions.
Address [35:32]
Other
0x0
0x1
0x4
0x5
0x6
Description
Intentionally unallocated
OCD registers
HSB memory space, as seen by the CPU
Alternative mapping for HSB space, for compatibility with
other 32-bit AVR devices.
Memory Service Unit registers
Unused
AT32UC3B
Table 27-1
583
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