AT32UC3B1256-AUT Atmel, AT32UC3B1256-AUT Datasheet - Page 325
![IC MCU AVR32 256KB FLASH 48-TQFP](/photos/6/82/68248/313-48-vqfp_sml.jpg)
AT32UC3B1256-AUT
Manufacturer Part Number
AT32UC3B1256-AUT
Description
IC MCU AVR32 256KB FLASH 48-TQFP
Manufacturer
Atmel
Series
AVR®32 UC3r
Specifications of AT32UC3B1256-AUT
Core Processor
AVR
Core Size
32-Bit
Speed
60MHz
Connectivity
I²C, IrDA, SPI, SSC, UART/USART, USB
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
28
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Data Converters
A/D 6x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
48-TQFP, 48-VQFP
Processor Series
AT32UC3x
Core
AVR32
Data Bus Width
32 bit
Data Ram Size
32 KB
Interface Type
2-Wire/SPI/USART
Maximum Clock Frequency
60 MHz
Number Of Programmable I/os
28
Number Of Timers
3
Operating Supply Voltage
3.3 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR32, EWAVR32-BL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATEXTWIFI, ATEVK1101
Minimum Operating Temperature
- 40 C
On-chip Adc
6-ch x 10-bit
Controller Family/series
AVR UC3
No. Of I/o's
28
Ram Memory Size
32KB
Cpu Speed
60MHz
No. Of Timers
1
Rohs Compliant
Yes
For Use With
ATSTK600-TQFP48 - STK600 SOCKET/ADAPTER 48-TQFPATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMR770-1008 - ISP 4PORT ATMEL AVR32 MCU SPIATEVK1101 - KIT DEV/EVAL FOR AVR32 AT32UC3B
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
AT32UC3B1256-AUT
Manufacturer:
ATMEL
Quantity:
1 000
- Current page: 325 of 692
- Download datasheet (11Mb)
21.6.4.6
21.6.4.7
21.6.5
32059K–03/2011
IrDA Mode
Disable Successive Receive NACK
Protocol T = 1
The ITERATION bit in CSR can be cleared by writing the Control Register with the RSIT bit at 1.
The receiver can limit the number of successive NACKs sent back to the remote transmitter.
This is programmed by setting the bit DSNACK in the Mode Register (MR). The maximum num-
ber of NACK transmitted is programmed in the MAX_ITERATION field. As soon as
MAX_ITERATION is reached, the character is considered as correct, an acknowledge is sent on
the line and the ITERATION bit in the Channel Status Register is set.
When operating in ISO7816 protocol T = 1, the transmission is similar to an asynchronous for-
mat with only one stop bit. The parity is generated when transmitting and checked when
receiving. Parity error detection sets the PARE bit in the Channel Status Register (CSR).
The USART features an IrDA mode supplying half-duplex point-to-point wireless communica-
tion. It embeds the modulator and demodulator which allows a glueless connection to the
infrared transceivers, as shown in
with the IrDA specification version 1.1 and support data transfer speeds ranging from 2.4 Kb/s to
115.2 Kb/s.
The USART IrDA mode is enabled by setting the MODE field in the Mode Register (MR) to the
value 0x8. The IrDA Filter Register (IFR) allows configuring the demodulator filter. The USART
transmitter and receiver operate in a normal asynchronous mode and all parameters are acces-
sible (except those fixed by IrDA specification: one start bit, 8 data bits and one stop bit). Note
that the modulator and the demodulator are activated.
Figure 21-32. Connection to IrDA Transceivers
The receiver and the transmitter must be enabled or disabled according to the direction of the
transmission to be managed.
To receive IrDA signals, the following needs to be done:
• Disable TX and Enable RX
• Configure the TXD pin as I/O and set it as an output at 0 (to avoid LED emission). Disable the
• Receive data
internal pull-up (better for power consumption).
Transmitter
Receiver
USART
Demodulator
Figure
Modulator
21-32. The modulator and demodulator are compliant
RXD
TXD
RX
TX
Transceivers
AT32UC3B
IrDA
325
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