AT91SAM7X512-AU-999 Atmel, AT91SAM7X512-AU-999 Datasheet - Page 104
AT91SAM7X512-AU-999
Manufacturer Part Number
AT91SAM7X512-AU-999
Description
IC MCU ARM 512K HS FLASH 100LQFP
Manufacturer
Atmel
Series
AT91SAMr
Datasheet
1.AT91SAM7X512-AU-999.pdf
(687 pages)
Specifications of AT91SAM7X512-AU-999
Core Processor
ARM7
Core Size
16/32-Bit
Speed
55MHz
Connectivity
CAN, Ethernet, I²C, SPI, SSC, UART/USART, USB
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
62
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
128K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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19.2.2
104
AT91SAM7X512/256/128 Preliminary
Read Operations
Figure 19-1. Embedded Flash Memory Mapping
An optimized controller manages embedded Flash reads. A system of 2 x 32-bit buffers is added
in order to start access at following address during the second read, thus increasing perfor-
mance when the processor is running in Thumb mode (16-bit instruction set). See
Figure 19-3
This optimization concerns only Code Fetch and not Data.
The read operations can be performed with or without wait state. Up to 3 wait states can be pro-
grammed in the field FWS (Flash Wait State) in the Flash Mode Register MC_FMR (see
Flash Mode Register” on page
the embedded Flash.
The Flash memory is accessible through 8-, 16- and 32-bit reads.
As the Flash block size is smaller than the address space reserved for the internal memory area,
the embedded Flash wraps around the address space and appears to be repeated within it.
and
Start Address
Figure
19-4.
Lock Region (n-1)
Flash Memory
Lock Region 0
Lock Region 1
114). Defining FWS to be 0 enables the single-cycle access of
32-bit wide
Lock Bit n-1
Lock Bit 0
Lock Bit 1
Page ( (n-1)*m )
Page (n*m-1)
Page (m-1)
Page 0
6120H–ATARM–17-Feb-09
Figure
19-2,
“MC
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