AT91SAM7X512-AU-999 Atmel, AT91SAM7X512-AU-999 Datasheet - Page 60
AT91SAM7X512-AU-999
Manufacturer Part Number
AT91SAM7X512-AU-999
Description
IC MCU ARM 512K HS FLASH 100LQFP
Manufacturer
Atmel
Series
AT91SAMr
Datasheet
1.AT91SAM7X512-AU-999.pdf
(687 pages)
Specifications of AT91SAM7X512-AU-999
Core Processor
ARM7
Core Size
16/32-Bit
Speed
55MHz
Connectivity
CAN, Ethernet, I²C, SPI, SSC, UART/USART, USB
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
62
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
128K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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13.2.4
13.2.4.1
Figure 13-4. Power-up Reset
60
AT91SAM7X512/256/128 Preliminary
periph_nreset
Reset States
Main Supply
POR output
proc_nreset
(nrst_out)
Power-up Reset
SLCK
NRST
MCK
The Reset State Manager handles the different reset sources and generates the internal reset
signals. It reports the reset status in the field RSTTYP of the Status Register (RSTC_SR). The
update of the field RSTTYP is performed when the processor reset is released.
When VDDCORE is powered on, the Main Supply POR cell output is filtered with a start-up
counter that operates at Slow Clock. The purpose of this counter is to ensure that the Slow
Clock oscillator is stable before starting up the device.
The startup time, as shown in
startup time. After the startup time, the reset signals are released and the field RSTTYP in
RSTC_SR reports a Power-up Reset.
When VDDCORE is detected low by the Main Supply POR Cell, all reset signals are asserted
immediately.
Startup Time
Figure
Processor Startup
EXTERNAL RESET LENGTH
= 3 cycles
13-4, is hardcoded to comply with the Slow Clock Oscillator
= 2 cycles
Freq.
Any
6120H–ATARM–17-Feb-09
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