AT91SAM7X512-AU-999 Atmel, AT91SAM7X512-AU-999 Datasheet - Page 488

IC MCU ARM 512K HS FLASH 100LQFP

AT91SAM7X512-AU-999

Manufacturer Part Number
AT91SAM7X512-AU-999
Description
IC MCU ARM 512K HS FLASH 100LQFP
Manufacturer
Atmel
Series
AT91SAMr
Datasheet

Specifications of AT91SAM7X512-AU-999

Core Processor
ARM7
Core Size
16/32-Bit
Speed
55MHz
Connectivity
CAN, Ethernet, I²C, SPI, SSC, UART/USART, USB
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
62
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
128K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
100-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-

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Part Number:
AT91SAM7X512-AU-999
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Quantity:
10 000
35.5.4
Figure 35-2. EOCx and DRDY Flag Behavior
488
(ADC_CHSR)
(ADC_SR)
(ADC_SR)
EOCx
DRDY
CHx
AT91SAM7X512/256/128 Preliminary
Conversion Results
Write the ADC_CR
with START = 1
When a conversion is completed, the resulting 10-bit digital value is stored in the Channel Data
Register (ADC_CDR) of the current channel and in the ADC Last Converted Data Register
(ADC_LCDR).
The channel EOC bit in the Status Register (ADC_SR) is set and the DRDY is set. In the case of
a connected PDC channel, DRDY rising triggers a data transfer request. In any case, either
EOC and DRDY can trigger an interrupt.
Reading one of the ADC_CDR registers clears the corresponding EOC bit. Reading ADC_LCDR
clears the DRDY bit and the EOC bit corresponding to the last converted channel.
Conversion Time
Read the ADC_CDRx
Write the ADC_CR
with START = 1
Conversion Time
Read the ADC_LCDR
6120H–ATARM–17-Feb-09

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