AT91SAM9260B-QU Atmel, AT91SAM9260B-QU Datasheet - Page 206

• Manufacturer Part Number: AT91SAM9260B-QU
• Description: IC ARM9 MCU 208-PQFP
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM9260B-QU

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 180MHz
• Connectivity: EBI/EMI, Ethernet, I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: POR, WDT
• Number Of I /o: 96
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: ROM
• Ram Size: 24K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 208-MQFP, 208-PQFP
• Package: 208PQFP
• Device Core: ARM926EJ-S
• Family Name: 91S
• Maximum Speed: 180 MHz
• Operating Supply Voltage: 1.8|3.3 V
• Data Bus Width: 32 Bit
• Number Of Programmable I/os: 96
• Interface Type: EBI/Ethernet/SPI/TWI/UART/USART/USB
• On-chip Adc: 4-chx10-bit
• Number Of Timers: 6
• Processor Series: AT91SAMx
• Core: ARM926EJ-S
• Data Ram Size: 8 KB
• Maximum Clock Frequency: 180 MHz
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: AT91SAM-ICE, AT91-ISP, AT91SAM9260-EK
• Minimum Operating Temperature: - 40 C
• Cpu Family: AT91
• Device Core Size: 32b
• Frequency (max): 180MHz
• Total Internal Ram Size: 8KB
• # I/os (max): 96
• Number Of Timers - General Purpose: 6
• Operating Supply Voltage (typ): 1.8/3.3V
• Operating Supply Voltage (max): 1.95/3.6V
• Operating Supply Voltage (min): 1.65/3V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 208
• Package Type: PQFP
• For Use With: AT91SAM9260-EK - KIT EVAL FOR AT91SAM9260AT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

6221I–ATARM–17-Jul-09
After initialization, the SDRAM devices are fully functional.
Note:
6. An All Banks Precharge command is issued to the SDRAM devices. The application
7. Eight auto-refresh (CBR) cycles are provided. The application must set the Mode to 4 in
8. A Mode Register set (MRS) cycle is issued to program the parameters of the SDRAM
9. For mobile SDRAM initialization, an Extended Mode Register set (EMRS) cycle is
10. The application must go into Normal Mode, setting Mode to 0 in the Mode Register and
11. Write the refresh rate into the count field in the SDRAMC Refresh Timer register.
must set Mode to 2 in the Mode Register and perform a write access to any SDRAM
address.
the Mode Register and perform a write access to any SDRAM location eight times.
devices, in particular CAS latency and burst length. The application must set Mode to 3
in the Mode Register and perform a write access to the SDRAM. The write address
must be chosen so that BA[1:0] are set to 0. For example, with a 16-bit 128 MB SDRAM
(12 rows, 9 columns, 4 banks) bank address, the SDRAM write access should be done
at the address 0x20000000.
issued to program the SDRAM parameters (TCSR, PASR, DS). The application must
set Mode to 5 in the Mode Register and perform a write access to the SDRAM. The
write address must be chosen so that BA[1] or BA[0] are set to 1. For example, with a
16-bit 128 MB SDRAM, (12 rows, 9 columns, 4 banks) bank address the SDRAM write
access should be done at the address 0x20800000 or 0x20400000.
performing a write access at any location in the SDRAM.
(Refresh rate = delay between refresh cycles). The SDRAM device requires a refresh
every 15.625 µs or 7.81 µs. With a 100 MHz frequency, the Refresh Timer Counter
Register must be set with the value 1562(15.652 µs x 100 MHz) or 781(7.81 µs x 100
MHz).
1. It is strongly recommended to respect the instructions stated in
cess in order to be certain that the subsequent commands issued by the SDRAMC will be
taken into account.
AT91SAM9260
Step 5
of the initialization pro-
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