AT91SAM9260B-QU Atmel, AT91SAM9260B-QU Datasheet - Page 40

• Manufacturer Part Number: AT91SAM9260B-QU
• Description: IC ARM9 MCU 208-PQFP
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM9260B-QU

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 180MHz
• Connectivity: EBI/EMI, Ethernet, I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: POR, WDT
• Number Of I /o: 96
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: ROM
• Ram Size: 24K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 208-MQFP, 208-PQFP
• Package: 208PQFP
• Device Core: ARM926EJ-S
• Family Name: 91S
• Maximum Speed: 180 MHz
• Operating Supply Voltage: 1.8|3.3 V
• Data Bus Width: 32 Bit
• Number Of Programmable I/os: 96
• Interface Type: EBI/Ethernet/SPI/TWI/UART/USART/USB
• On-chip Adc: 4-chx10-bit
• Number Of Timers: 6
• Processor Series: AT91SAMx
• Core: ARM926EJ-S
• Data Ram Size: 8 KB
• Maximum Clock Frequency: 180 MHz
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: AT91SAM-ICE, AT91-ISP, AT91SAM9260-EK
• Minimum Operating Temperature: - 40 C
• Cpu Family: AT91
• Device Core Size: 32b
• Frequency (max): 180MHz
• Total Internal Ram Size: 8KB
• # I/os (max): 96
• Number Of Timers - General Purpose: 6
• Operating Supply Voltage (typ): 1.8/3.3V
• Operating Supply Voltage (max): 1.95/3.6V
• Operating Supply Voltage (min): 1.65/3V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 208
• Package Type: PQFP
• For Use With: AT91SAM9260-EK - KIT EVAL FOR AT91SAM9260AT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

10.4.9
10.4.10
40
AT91SAM9260
New ARM Instruction Set
Thumb Instruction Set Overview
Table 10-3.
Notes:
The Thumb instruction set is a re-encoded subset of the ARM instruction set.
The Thumb instruction set is divided into:
Table 10-4
Table 10-4.
Mnemonic
Mnemonic
MOV
ADD
SUB
CMP
TST
AND
EOR
• Branch instructions
• Data processing instructions
• Load and Store instructions
• Load and Store multiple instructions
• Exception-generating instruction
SMLAWy
SMULWy
SMULxy
SMLAxy
QDADD
QDSUB
BLX
SMLAL
QADD
QSUB
BXJ
1. A Thumb BLX contains two consecutive Thumb instructions, and takes four cycles.
(1)
gives the Thumb instruction mnemonic list.
New ARM Instruction Mnemonic List
Thumb Instruction Mnemonic List
Operation
Move
Add
Subtract
Compare
Test
Logical AND
Logical Exclusive OR
Operation
Branch and exchange to Java
Branch, Link and exchange
Signed Multiply Accumulate 16
* 16 bit
Signed Multiply Accumulate
Long
Signed Multiply Accumulate 32
* 16 bit
Signed Multiply 16 * 16 bit
Signed Multiply 32 * 16 bit
Saturated Add
Saturated Add with Double
Saturated subtract
Saturated Subtract with double
Mnemonic
Mnemonic
MVN
ADC
SBC
CMN
NEG
BIC
ORR
MRRC
MCRR
MCR2
STRD
LDRD
CDP2
BKPT
STC2
LDC2
PLD
CLZ
Operation
Move Not
Add with Carry
Subtract with Carry
Compare Negated
Negate
Bit Clear
Logical (inclusive) OR
Operation
Move double to coprocessor
Breakpoint
Store Double
Load Double
Count Leading Zeroes
Move double from coprocessor
Alternative move of ARM reg to
coprocessor
Alternative Coprocessor Data
Processing
Soft Preload, Memory prepare
to load from address
Alternative Store from
Coprocessor
Coprocessor
Alternative Load to
6221I–ATARM–17-Jul-09