AT91SAM9260B-QU Atmel, AT91SAM9260B-QU Datasheet - Page 357
![IC ARM9 MCU 208-PQFP](/photos/6/73/67311/313-208-pqfp_sml.jpg)
AT91SAM9260B-QU
Manufacturer Part Number
AT91SAM9260B-QU
Description
IC ARM9 MCU 208-PQFP
Manufacturer
Atmel
Series
AT91SAMr
Specifications of AT91SAM9260B-QU
Core Processor
ARM9
Core Size
16/32-Bit
Speed
180MHz
Connectivity
EBI/EMI, Ethernet, I²C, MMC, SPI, SSC, UART/USART, USB
Peripherals
POR, WDT
Number Of I /o
96
Program Memory Size
32KB (32K x 8)
Program Memory Type
ROM
Ram Size
24K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 1.95 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
208-MQFP, 208-PQFP
Package
208PQFP
Device Core
ARM926EJ-S
Family Name
91S
Maximum Speed
180 MHz
Operating Supply Voltage
1.8|3.3 V
Data Bus Width
32 Bit
Number Of Programmable I/os
96
Interface Type
EBI/Ethernet/SPI/TWI/UART/USART/USB
On-chip Adc
4-chx10-bit
Number Of Timers
6
Processor Series
AT91SAMx
Core
ARM926EJ-S
Data Ram Size
8 KB
Maximum Clock Frequency
180 MHz
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
Development Tools By Supplier
AT91SAM-ICE, AT91-ISP, AT91SAM9260-EK
Minimum Operating Temperature
- 40 C
Cpu Family
AT91
Device Core Size
32b
Frequency (max)
180MHz
Total Internal Ram Size
8KB
# I/os (max)
96
Number Of Timers - General Purpose
6
Operating Supply Voltage (typ)
1.8/3.3V
Operating Supply Voltage (max)
1.95/3.6V
Operating Supply Voltage (min)
1.65/3V
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
208
Package Type
PQFP
For Use With
AT91SAM9260-EK - KIT EVAL FOR AT91SAM9260AT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
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29. Serial Peripheral Interface (SPI)
29.1
29.2
6221I–ATARM–17-Jul-09
Description
Embedded Characteristics
The Serial Peripheral Interface (SPI) circuit is a synchronous serial data link that provides com-
munication with external devices in Master or Slave Mode. It also enables communication
between processors if an external processor is connected to the system.
The Serial Peripheral Interface is essentially a shift register that serially transmits data bits to
other SPIs. During a data transfer, one SPI system acts as the “master”' which controls the data
flow, while the other devices act as “slaves'' which have data shifted into and out by the master.
Different CPUs can take turn being masters (Multiple Master Protocol opposite to Single Master
Protocol where one CPU is always the master while all of the others are always slaves) and one
master may simultaneously shift data into multiple slaves. However, only one slave may drive its
output to write data back to the master at any given time.
A slave device is selected when the master asserts its NSS signal. If multiple slave devices
exist, the master generates a separate slave select signal for each slave (NPCS).
The SPI system consists of two data lines and two control lines:
• Master Out Slave In (MOSI): This data line supplies the output data from the master shifted
• Master In Slave Out (MISO): This data line supplies the output data from a slave to the input
• Serial Clock (SPCK): This control line is driven by the master and regulates the flow of the
• Slave Select (NSS): This control line allows slaves to be turned on and off by hardware.
• Supports communication with serial external devices
• Master or slave serial peripheral bus interface
• Very fast transfers supported
into the input(s) of the slave(s).
of the master. There may be no more than one slave transmitting data during any particular
transfer.
data bits. The master may transmit data at a variety of baud rates; the SPCK line cycles once
for each bit that is transmitted.
– Four chip selects with external decoder support allow communication with up to 15
– Serial memories, such as DataFlash and 3-wire EEPROMs
– Serial peripherals, such as ADCs, DACs, LCD Controllers, CAN Controllers and
– External co-processors
– 8- to 16-bit programmable data length per chip select
– Programmable phase and polarity per chip select
– Programmable transfer delays between consecutive transfers and between clock
– Programmable delay between consecutive transfers
– Selectable mode fault detection
– Transfers with baud rates up to MCK
peripherals
Sensors
and data per chip select
AT91SAM9260
357
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