AT91SAM9XE256-CU Atmel, AT91SAM9XE256-CU Datasheet - Page 665

• Manufacturer Part Number: AT91SAM9XE256-CU
• Description: MCU ARM9 256K FLASH 217-BGA
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM9XE256-CU

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 180MHz
• Connectivity: EBI/EMI, Ethernet, I²C, MMC, SPI, SSC, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 56K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 4x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 217-LFBGA
• Processor Series: AT91SAMx
• Core: ARM926EJ-S
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: 2-Wire, EBI, I2S, SPI, USART
• Maximum Clock Frequency: 180 MHz
• Number Of Programmable I/os: 96
• Number Of Timers: 6
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-ARM-2M, KSK-AT91SAM9XE-PL, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: AT91SAM-ICE, AT91-ISP, AT91SAM9XE-EK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 4 Channel
• Package: 217LFBGA
• Device Core: ARM926EJ-S
• Family Name: 91S
• Maximum Speed: 180 MHz
• Operating Supply Voltage: 1.8|2.5|3.3 V
• For Use With: AT91SAM9XE-EK - KIT EVAL FOR AT91SAM9XEAT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Table 38-2.
38.3.3
6254C–ATARM–22-Jan-10
Bit
26:17
14:11
10:0
31
30
29
28
27
16
15
Transmit Block
Used. Needs to be zero for the EMAC to read data from the transmit buffer. The EMAC sets this to one for the first buffer
of a frame once it has been successfully transmitted.
Software has to clear this bit before the buffer can be used again.
Note:
Wrap. Marks last descriptor in transmit buffer descriptor list.
Retry limit exceeded, transmit error detected
Transmit underrun, occurs either when hresp is not OK (bus error) or the transmit data could not be fetched in time or
when buffers are exhausted in mid frame.
Buffers exhausted in mid frame
Reserved
No CRC. When set, no CRC is appended to the current frame. This bit only needs to be set for the last buffer of a frame.
Last buffer. When set, this bit indicates the last buffer in the current frame has been reached.
Reserved
Length of buffer
Transmit Buffer Descriptor Entry
This bit is only set for the first buffer in a frame unlike receive where all buffers have the Used bit set once used.
This block transmits frames in accordance with the Ethernet IEEE 802.3 CSMA/CD protocol.
Frame assembly starts by adding preamble and the start frame delimiter. Data is taken from the
transmit FIFO a word at a time. Data is transmitted least significant nibble first. If necessary,
padding is added to increase the frame length to 60 bytes. CRC is calculated as a 32-bit polyno-
mial. This is inverted and appended to the end of the frame, taking the frame length to a
minimum of 64 bytes. If the No CRC bit is set in the second word of the last buffer descriptor of a
transmit frame, neither pad nor CRC are appended.
In full-duplex mode, frames are transmitted immediately. Back-to-back frames are transmitted at
least 96 bit times apart to guarantee the interframe gap.
In half-duplex mode, the transmitter checks carrier sense. If asserted, it waits for it to de-assert
and then starts transmission after the interframe gap of 96 bit times. If the collision signal is
asserted during transmission, the transmitter transmits a jam sequence of 32 bits taken from the
data register and then retry transmission after the back off time has elapsed.
The back-off time is based on an XOR of the 10 least significant bits of the data coming from the
transmit FIFO and a 10-bit pseudo random number generator. The number of bits used depends
on the number of collisions seen. After the first collision, 1 bit is used, after the second 2, and so
on up to 10. Above 10, all 10 bits are used. An error is indicated and no further attempts are
made if 16 attempts cause collisions.
If transmit DMA underruns, bad CRC is automatically appended using the same mechanism as
jam insertion and the tx_er signal is asserted. For a properly configured system, this should
never happen.
If the back pressure bit is set in the network control register in half duplex mode, the transmit
block transmits 64 bits of data, which can consist of 16 nibbles of 1011 or in bit-rate mode 64 1s,
AT91SAM9XE128/256/512 Preliminary
Function
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