P89LPC9151FDH,129 NXP Semiconductors, P89LPC9151FDH,129 Datasheet - Page 40

• Manufacturer Part Number: P89LPC9151FDH,129
• Description: IC 80C51 MCU FLASH 2KB 14TSSOP
• Manufacturer: NXP Semiconductors
• Series: LPC900r

Specifications of P89LPC9151FDH,129

• Program Memory Type: FLASH
• Program Memory Size: 2KB (2K x 8)
• Package / Case: 14-TSSOP
• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 18MHz
• Connectivity: I²C, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 12
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Data Converters: A/D 4x8b; D/A 1x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: P89LPC
• Core: 80C51
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: SPI
• Maximum Clock Frequency: 18 MHz
• Number Of Programmable I/os: 10
• Number Of Timers: 2
• Operating Supply Voltage: 2.4 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit, 4 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 935290259129

NXP Semiconductors
P89LPC9151_61_71_2
Product data sheet
7.10 CCLK modification: DIVM register
7.11 Low power select
7.9 CCLK wake-up delay
The P89LPC9151/9161/9171 has an internal wake-up timer that delays the clock until it
stabilizes depending on the clock source used. If the clock source is any of the three
crystal selections (low, medium and high frequencies) the delay is 1024 OSCCLK cycles
plus 60 μs to 100 μs. If the clock source is the internal RC oscillator, the delay is 200 μs to
300 μs. If the clock source is watchdog oscillator or external clock, the delay is
32 OSCCLK cycles.
The OSCCLK frequency can be divided down up to 510 times by configuring a dividing
register, DIVM, to generate CCLK. This feature makes it possible to temporarily run the
CPU at a lower rate, reducing power consumption. By dividing the clock, the CPU can
retain the ability to respond to events that would not exit Idle mode by executing its normal
program at a lower rate. This can also allow bypassing the oscillator start-up time in cases
where Power-down mode would otherwise be used. The value of DIVM may be changed
by the program at any time without interrupting code execution.
The P89LPC9151/9161/9171 is designed to run at 18 MHz (CCLK) maximum. However, if
CCLK is 8 MHz or slower, the CLKLP SFR bit (AUXR1.7) can be set to logic 1 to lower the
power consumption further. On any reset, CLKLP is logic 0 allowing highest performance
access. This bit can then be set in software if CCLK is running at 8 MHz or slower.
Rev. 02 — 9 February 2010
P89LPC9151/9161/9171
8-bit microcontroller with 8-bit ADC
© NXP B.V. 2010. All rights reserved.
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