LPC3143FET180,551 NXP Semiconductors, LPC3143FET180,551 Datasheet
LPC3143FET180,551
Manufacturer Part Number
LPC3143FET180,551
Description
IC ARM9 MCU USB OTG 180TFBGA
Manufacturer
NXP Semiconductors
Series
LPC3000r
Datasheet
1.LPC3143FET180551.pdf
(74 pages)
Specifications of LPC3143FET180,551
Package / Case
180-TFBGA
Voltage - Supply (vcc/vdd)
1.1 V ~ 1.3 V
Operating Temperature
-40°C ~ 85°C
Speed
270MHz
Number Of I /o
20
Core Processor
ARM9
Program Memory Type
External Program Memory
Ram Size
192K x 8
Data Converters
A/D 4x10b
Oscillator Type
External
Peripherals
DMA, I²S, LCD, PWM, WDT
Connectivity
EBI/EMI, I²C, IrDA, MMC, PCM, SPI, UART/USART, USB OTG
Core Size
32-Bit
Processor Series
LPC31
Core
ARM926EJ-S
Data Bus Width
32 bit
Data Ram Size
192 KB
Interface Type
I2C, I2S, SPI, JTAG, UART, USB
Maximum Clock Frequency
270 MHz
Number Of Timers
5
Operating Supply Voltage
1.2 V, 1.8 V, 3.3 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 4 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Details
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1. General description
2. Features and benefits
2.1 Key features
The NXP LPC3141/3143 combine a 270 MHz ARM926EJ-S CPU core, High-speed USB
2.0 OTG, 192 KB SRAM, NAND flash controller, flexible external bus interface, four
channel 10-bit A/D, and a myriad of serial and parallel interfaces in a single chip targeted
at consumer, industrial, medical, and communication markets. To optimize system power
consumption, the LPC3141/3143 have multiple power domains and a very flexible Clock
Generation Unit (CGU) that provides dynamic clock gating and scaling.
LPC3141/3143
Low-cost, low-power ARM926EJ microcontrollers with USB
High-speed OTG, SD/MMC, and NAND flash controller
Rev. 0.16 — 27 May 2010
CPU platform
Internal memory
External memory interface
Security
Communication and connectivity
System functions
270 MHz, 32-bit ARM926EJ-S
16 kB D-cache and 16 kB I-cache
Memory Management Unit (MMU)
192 kB embedded SRAM
NAND flash controller with 8-bit ECC and AES decryption support (LPC3143 only)
8/16-bit Multi-Port Memory Controller (MPMC): SDRAM and SRAM
AES decryption engine (LPC3143 only)
Secure one-time programmable memory for AES key storage and customer use
128 bit unique ID per device for DRM schemes
High-speed USB 2.0 (OTG, Host, Device) with on-chip PHY
Two I
Integrated master/slave SPI
Two master/slave I
Fast UART
Memory Card Interface (MCI): MMC/SD/SDIO/CE-ATA
Four-channel 10-bit ADC
Integrated 4/8/16-bit 6800/8080 compatible LCD interface
Dynamic clock gating and scaling
Multiple power domains
2
S interfaces
2
C-bus interfaces
Preliminary data sheet
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