Z8F082AHH020SG2156 Zilog, Z8F082AHH020SG2156 Datasheet - Page 67
Z8F082AHH020SG2156
Manufacturer Part Number
Z8F082AHH020SG2156
Description
IC ENCORE XP MCU FLASH 8K
Manufacturer
Zilog
Series
Encore!® XP®r
Datasheet
1.Z8F082AHH020SG2156.pdf
(240 pages)
Specifications of Z8F082AHH020SG2156
Core Processor
Z8
Core Size
8-Bit
Speed
20MHz
Connectivity
IrDA, UART/USART
Peripherals
Brown-out Detect/Reset, LED, LVD, POR, PWM, Temp Sensor, WDT
Number Of I /o
17
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 7x10b
Oscillator Type
Internal
Operating Temperature
0°C ~ 70°C
Package / Case
20-SSOP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Other names
Q5278375
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ADCX
Add with Carry using Extended Addressing
ADCX dst, src
UM012811-0904
Mnemonic Destination, Source
ADCX
ADCX
Operation
Description
Flags
Attributes
Escaped Mode Addressing
ER1, ER2
ER1, IM
dst
Add the source operand and the Carry (C) flag to the destination operand. Perform two’s-
complement addition. Store the sum in the destination operand. The contents of the source
operand are not affected. In multiple-precision (multi-byte) arithmetic, this instruction
permits the carry from the addition of low-order byte operations to be carried into the
addition of high-order bytes. The destination and source operands use 12-bit addresses to
access any address in the Register File.
Using Escaped Mode Addressing, address mode ER for the source or destination can spec-
ify a Working Register with 4-bit addressing.
If the high byte of the source or destination address is
ter is inferred. For example, the operand
bit address is given by {RP[3:0], RP[7:4], 3H}.
To access Registers on Page EH (addresses
to
C
Z
S
V
D
H
EH
←
and set the Working Group Pointer, RP[7:4], to the desired Working Group.
dst + src + C
Set if there is a carry from bit 7; reset otherwise.
Set if the result is zero; reset otherwise.
Set if the result is negative; reset otherwise.
Set if an arithmetic overflow occurs; reset otherwise.
Reset to 0.
Set if there is a carry from bit 3 of the result; reset otherwise.
Opcode (Hex)
18
19
Operand 1
ER2[11:4]
IM
EE3H
E00H
selects Working Register R3. The full 12-
to
Operand 2
{ER2[3:0], ER1[11:8]} ER1[7:0]
{0H, ER1[11:8]}
EFFH
eZ8 CPU Instruction Set Description
EEH
), set the Page Pointer, RP[3:0],
(11101110B), a Working Regis-
Operand 3
ER1[7:0]
User Manual
eZ8 CPU
57
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