ST7FOXK1T6 STMicroelectronics, ST7FOXK1T6 Datasheet - Page 146

• Manufacturer Part Number: ST7FOXK1T6
• Description: IC MCU 8BIT 1V FLASH MEM 32LQFP
• Manufacturer: STMicroelectronics
• Series: ST7r

Specifications of ST7FOXK1T6

• Core Processor: ST7
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: I²C
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 4KB (4K x 8)
• Program Memory Type: FLASH
• Ram Size: 384 x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 10x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-LQFP
• Processor Series: ST7FOXx
• Core: ST7
• Data Bus Width: 8 bit
• Data Ram Size: 384 B
• Interface Type: I2C
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: ST7FLITE-SK/RAIS, STX-RLINK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 1 Channel
• For Use With: 497-5049 - KIT STARTER RAISONANCE ST7FLITE
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 497-6336

On-chip peripherals
Master mode
Note:
Note:
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To switch from default Slave mode to Master mode a Start condition generation is needed.
Start condition
Setting the START bit while the BUSY bit is cleared causes the interface to switch to Master
mode (M/SL bit set) and generates a Start condition.
Once the Start condition is sent, the EVF and SB bits are set by hardware with an interrupt if
the ITE bit is set.
The master then waits for a read of the SR1 register followed by a write in the DR register
with the Slave address, holding the SCL line low (see
EV5).
Slave address transmission
1.
2.
3.
4.
5.
6.
In 10-bit addressing mode, to switch the master to Receiver mode, software must generate
a repeated Start condition and resend the header sequence with the least significant bit set
(11110xx1).
Master receiver
Following the address transmission and after SR1 and CR registers have been accessed,
the master receives bytes from the SDA line into the DR register via the internal shift
register. After each byte the interface generates in sequence:
Then the interface waits for a read of the SR1 register followed by a read of the DR register,
holding the SCL line low (see
To close the communication: before reading the last byte from the DR register, set the STOP
bit to generate the Stop condition. The interface goes automatically back to slave mode
(M/SL bit cleared).
In order to generate the non-acknowledge pulse after the last received data byte, the ACK
bit must be cleared just before reading the second last data byte.
The slave address is then sent to the SDA line via the internal shift register.
–
–
The master then waits for a read of the SR1 register followed by a write in the DR
register, holding the SCL line low (see
Then the second address byte is sent by the interface.
After completion of this transfer (and acknowledge from the slave if the ACK bit is set),
the EVF bit is set by hardware with interrupt generation if the ITE bit is set.
The master waits for a read of the SR1 register followed by a write in the CR register
(for example set PE bit), holding the SCL line low (see
EV6).
Next the master must enter Receiver or Transmitter mode.
Acknowledge pulse if the ACK bit is set
EVF and BTF bits are set by hardware with an interrupt if the ITE bit is set.
In 7-bit addressing mode, one address byte is sent.
In 10-bit addressing mode, sending the first byte including the header sequence
causes the following event. The EVF bit is set by hardware with interrupt
generation if the ITE bit is set.
Figure 71
Transfer sequencing EV7).
Figure 71
ST7FOXF1, ST7FOXK1, ST7FOXK2
Transfer sequencing EV9).
Figure 71
Figure 71
Transfer sequencing
Transfer sequencing