Z8F2422VS020SG Zilog, Z8F2422VS020SG Datasheet - Page 168

• Manufacturer Part Number: Z8F2422VS020SG
• Description: IC ENCORE MCU FLASH 24K 68PLCC
• Manufacturer: Zilog
• Series: Encore!® XP®r

Specifications of Z8F2422VS020SG

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 46
• Program Memory Size: 24KB (24K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 68-LCC (J-Lead)
• Processor Series: Z8F242x
• Core: eZ8
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 46
• Number Of Timers: 4
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: Z8F64200100KITG, ZENETSC0100ZACG, ZUSBSC00100ZACG, Z8F64210100ZDA, Z8F64210100ZDP, Z8F64210100ZDV, Z8F64220100ZDA, Z8F64220100ZDV, Z8F6422AR00ZEM, Z8F6422VS00ZEM, Z8F6421AN00ZEM
• Minimum Operating Temperature: 0 C
• On-chip Adc: 10 bit, 12 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-4253; Z8F2422VS020SG

Table 72. I
PS019921-0308
BITS
FIELD
RESET
R/W
ADDR
Caution:
I
2
C Control Register
2
C Control Register (I2CCTL)
R/W
IEN
7
10B—10-Bit Address
This bit indicates whether a 10- or 7-bit address is being transmitted. After the START bit
is set, if the five most-significant bits of the address are 11110B, this bit is set. When set,
it is reset once the first byte of the address has been sent.
RD—Read
This bit indicates the direction of transfer of the data. It is active high during a read. The
status of this bit is determined by the least-significant bit of the I
START bit is set.
TAS—Transmit Address State
This bit is active high while the address is being shifted out of the I
DSS—Data Shift State
This bit is active high while data is being shifted to or from the I
NCKI—NACK Interrupt
This bit is set high when a Not Acknowledge condition is received or sent and neither the
START nor the STOP bit is active. When set, this bit generates an interrupt that can only
be cleared by setting the START or STOP bit, allowing you to specify whether to perform
a STOP or a repeated START.
The I
action because software cannot tell when the bit is updated by hardware. In the
case of write transactions, the I
cycle if the next transmit data or address byte has not been written (TDRE = 1)
and STOP and START = 0. In this case the ACK bit is not updated until the
transmit interrupt is serviced and the Acknowledge cycle for the previous byte
completes. For examples of how the ACK bit can be used, see
Transaction with a 7-bit Address
with a 10-bit Address
Software must be cautious in making decisions based on this bit within a trans-
2
C Control register
START
R/W1
6
STOP
R/W1
5
(Table
on page 146.
72) enables the I
BIRQ
R/W
2
4
C pauses at the beginning of the Acknowledge
on page 144 and
F52H
0
R/W
TXI
3
2
C operation.
Address Only Transaction
Z8 Encore! XP
R/W1
NAK
2
Product Specification
2
2
C Shift register after the
C Shift register.
Address Only
2
C Shift register.
FLUSH
W1
1
®
F64XX Series
I2C Controller
FILTEN
R/W
0
154