Z8F2422VS020SG Zilog, Z8F2422VS020SG Datasheet - Page 75

• Manufacturer Part Number: Z8F2422VS020SG
• Description: IC ENCORE MCU FLASH 24K 68PLCC
• Manufacturer: Zilog
• Series: Encore!® XP®r

Specifications of Z8F2422VS020SG

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 46
• Program Memory Size: 24KB (24K x 8)
• Program Memory Type: FLASH
• Ram Size: 2K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 68-LCC (J-Lead)
• Processor Series: Z8F242x
• Core: eZ8
• Data Bus Width: 8 bit
• Data Ram Size: 2 KB
• Interface Type: I2C, SPI, UART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 46
• Number Of Timers: 4
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: Z8F64200100KITG, ZENETSC0100ZACG, ZUSBSC00100ZACG, Z8F64210100ZDA, Z8F64210100ZDP, Z8F64210100ZDV, Z8F64220100ZDA, Z8F64220100ZDV, Z8F6422AR00ZEM, Z8F6422VS00ZEM, Z8F6421AN00ZEM
• Minimum Operating Temperature: 0 C
• On-chip Adc: 10 bit, 12 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 269-4253; Z8F2422VS020SG

Table 19. Port A–H High Drive Enable Sub-Registers
Table 20. Port A–H Stop Mode Recovery Source Enable Sub-Registers
PS019921-0308
BITS
FIELD
RESET
R/W
ADDR
BITS
FIELD
RESET
R/W
ADDR
PSMRE7
PHDE7
7
7
PHDE[7:0]—Port High Drive Enabled
0 = The Port pin is configured for standard output current drive.
1 = The Port pin is configured for high output current drive.
Port A
The Port A–H Stop Mode Recovery Source Enable sub-register
through the Port A–H Control register by writing
Setting the bits in the Port A–H Stop Mode Recovery Source Enable sub-registers to 1
configures the specified Port pins as a Stop Mode Recovery source. During STOP Mode,
any logic transition on a Port pin enabled as a Stop Mode Recovery source initiates Stop
Mode Recovery.
PSMRE[7:0]—Port Stop Mode Recovery Source Enabled
0 = The Port pin is not configured as a Stop Mode Recovery source. Transitions on this
1 = The Port pin is configured as a Stop Mode Recovery source. Any logic transition
If 05H in Port A
If 04H in Port A-H Address Register, accessible through Port A-H Control Register
pin during STOP mode do not initiate Stop Mode Recovery.
on this pin during STOP mode initiates Stop Mode Recovery.
PSMRE6
–
PHDE6
H Stop Mode Recovery Source Enable Sub-Registers
6
6
–
H Address Register, accessible through Port A
PSMRE5
PHDE5
5
5
PSMRE4
PHDE4
4
4
R/W
R/W
0
0
PSMRE3
PHDE3
3
3
05H
to the Port A–H Address register.
Z8 Encore! XP
PSMRE2
PHDE2
2
2
–
(Table
Product Specification
H Control Register
PSMRE1
PHDE1
20) is accessed
General-Purpose I/O
1
1
®
F64XX Series
PSMRE0
PHDE0
0
0
61