STR912FAW47X6 STMicroelectronics, STR912FAW47X6 Datasheet - Page 39

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STR912FAW47X6

Manufacturer Part Number
STR912FAW47X6
Description
MCU ARM9 2048KB FLASH 128LQFP
Manufacturer
STMicroelectronics
Series
STR9r
Datasheet

Specifications of STR912FAW47X6

Core Processor
ARM9
Core Size
32-Bit
Speed
96MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, IrDA, Microwire, SPI, SSI, SSP, UART/USART, USB
Peripherals
Brown-out Detect/Reset, DMA, Motor Control PWM, POR, PWM, WDT
Number Of I /o
80
Program Memory Size
2MB (2M x 8)
Program Memory Type
FLASH
Ram Size
96K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 2 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
128-LQFP
Processor Series
STR912x
Core
ARM966E-S
Data Bus Width
16 bit, 32 bit
Data Ram Size
96 KB
Interface Type
CAN, I2C, IrDA, SSP, UART, USB
Maximum Clock Frequency
96 MHz
Number Of Programmable I/os
80
Number Of Timers
4
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWARM, EWARM-BL, MCBSTR9, MCBSTR9U, MCBSTR9UME, KSDK-STR912-PLUS, MDK-ARM, RL-ARM, ULINK2
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
Cpu Family
STR9
Device Core
ARM966E-S
Device Core Size
16/32Bit
Frequency (max)
96MHz
Total Internal Ram Size
96KB
# I/os (max)
80
Number Of Timers - General Purpose
4
Operating Supply Voltage (typ)
1.8/3.3V
Operating Supply Voltage (max)
2/3.6V
Operating Supply Voltage (min)
1.65/1.77/2.5/2.7V
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
128
Package Type
LQFP
For Use With
MCBSTR9UME - BOARD EVAL MCBSTR9 + ULINK-MEMCBSTR9U - BOARD EVAL MCBSTR9 + ULINK2MCBSTR9 - BOARD EVAL STM STR9 SERIES
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
 Details
Other names
497-9039
STR912FAW47X6

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STR91xFAxxx
EMI_BWR_WRLn is the data write strobe, and the output on pin EMI_RDn is the data read
strobe.
8-bit non-multiplexed data mode
bits of address are output on ports 7 and 9. The output signal on pin EMI_BWR_BWLn
is the data write strobe and the output on pin EMI_RDn is the data read strobe.
Burst Mode Support (LFBGA package only): The EMI bus supports synchronized
burst read and write bus cycle in multiplexed and non-multiplexed mode. The additional
EMI signals in the LFBGA package that support the burst mode are:
By defining the bus parameters such as burst length, burst type, read and write timings
in the EMI control registers, the EMI bus is able to interface to standard burst memory
devices. The burst timing specification and waveform will be provided in the next data
sheet release
EMI_BCLK -the bus clock output. The EMI_BCLK has the same frequency or half
of that of the HCLK and can be disabled by the user
EMI_WAITn - the not ready or wait input signal for synchronous access
EMI_BAAn - burst address advance or burst enable signal
EMI_WEn - write enable signal
EMI_UBn, EMI_LBn - upper byte and lower byte enable signals. These two signals
share the same pins as the EMI_WRLn and EMI_WRHn and are user configurable
through the EMI register.
Doc ID 13495 Rev 6
(Figure
6): Eight bits of data are on port 8, while 16
Functional overview
39/102

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