STR912FAW47X6 STMicroelectronics, STR912FAW47X6 Datasheet - Page 63

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STR912FAW47X6

Manufacturer Part Number
STR912FAW47X6
Description
MCU ARM9 2048KB FLASH 128LQFP
Manufacturer
STMicroelectronics
Series
STR9r
Datasheet

Specifications of STR912FAW47X6

Core Processor
ARM9
Core Size
32-Bit
Speed
96MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, IrDA, Microwire, SPI, SSI, SSP, UART/USART, USB
Peripherals
Brown-out Detect/Reset, DMA, Motor Control PWM, POR, PWM, WDT
Number Of I /o
80
Program Memory Size
2MB (2M x 8)
Program Memory Type
FLASH
Ram Size
96K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 2 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
128-LQFP
Processor Series
STR912x
Core
ARM966E-S
Data Bus Width
16 bit, 32 bit
Data Ram Size
96 KB
Interface Type
CAN, I2C, IrDA, SSP, UART, USB
Maximum Clock Frequency
96 MHz
Number Of Programmable I/os
80
Number Of Timers
4
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWARM, EWARM-BL, MCBSTR9, MCBSTR9U, MCBSTR9UME, KSDK-STR912-PLUS, MDK-ARM, RL-ARM, ULINK2
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
Cpu Family
STR9
Device Core
ARM966E-S
Device Core Size
16/32Bit
Frequency (max)
96MHz
Total Internal Ram Size
96KB
# I/os (max)
80
Number Of Timers - General Purpose
4
Operating Supply Voltage (typ)
1.8/3.3V
Operating Supply Voltage (max)
2/3.6V
Operating Supply Voltage (min)
1.65/1.77/2.5/2.7V
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
128
Package Type
LQFP
For Use With
MCBSTR9UME - BOARD EVAL MCBSTR9 + ULINK-MEMCBSTR9U - BOARD EVAL MCBSTR9 + ULINK2MCBSTR9 - BOARD EVAL STM STR9 SERIES
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
 Details
Other names
497-9039
STR912FAW47X6

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STR91xFAxxx
7.5.1
LVD delay timing
Case 1: When V
(introduced by the VDD rising edge), a new ~10 ms delay starts before the release of
RESET_OUTn. See
Figure 12. LVD reset delay case 1
Case 2: When V
(introduced by the VDD rising edge), RESET_OUTn will be released immediately at the end
of the delay. No new delay is introduced in this case. See
Figure 13. LVD reset delay case 2
Case 3: When V
RESET_OUTn will be released at the end of a ~10 ms delay. See
Figure 14. LVD reset delay case 3
V
V
RESET_OUTn (blue)
V
V
V
V
RESET_OUTn (blue)
RESET_OUTn (blue)
DD
DDQ
DD
DDQ
DD
DDQ
(green)
(green)
(green)
(red)
(red)
(red)
V
DDQ
DDQ
DD
V
DD_LVD+
DD_LVD+
reaches the V
Figure 12.
reaches the V
reaches the V
V
V
~10 ms delay
DDQ_LVD+
DDQ_LVD+
~10 ms delay
Doc ID 13495 Rev 6
DD_LVD+
DDQ_LVD+
DDQ_LVD+
V
DD_LVD+
threshold after the V
threshold after the first ~10 ms delay
threshold before the first ~10 ms delay
~10 ms delay
Figure 13.
V
DDQ_LVD+
DDQ
Electrical characteristics
Figure 14
rising edge,
~10 ms delay
63/102

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