STR912FAW47X6 STMicroelectronics, STR912FAW47X6 Datasheet - Page 46

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STR912FAW47X6

Manufacturer Part Number
STR912FAW47X6
Description
MCU ARM9 2048KB FLASH 128LQFP
Manufacturer
STMicroelectronics
Series
STR9r
Datasheet

Specifications of STR912FAW47X6

Core Processor
ARM9
Core Size
32-Bit
Speed
96MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, IrDA, Microwire, SPI, SSI, SSP, UART/USART, USB
Peripherals
Brown-out Detect/Reset, DMA, Motor Control PWM, POR, PWM, WDT
Number Of I /o
80
Program Memory Size
2MB (2M x 8)
Program Memory Type
FLASH
Ram Size
96K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 2 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
128-LQFP
Processor Series
STR912x
Core
ARM966E-S
Data Bus Width
16 bit, 32 bit
Data Ram Size
96 KB
Interface Type
CAN, I2C, IrDA, SSP, UART, USB
Maximum Clock Frequency
96 MHz
Number Of Programmable I/os
80
Number Of Timers
4
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWARM, EWARM-BL, MCBSTR9, MCBSTR9U, MCBSTR9UME, KSDK-STR912-PLUS, MDK-ARM, RL-ARM, ULINK2
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
Cpu Family
STR9
Device Core
ARM966E-S
Device Core Size
16/32Bit
Frequency (max)
96MHz
Total Internal Ram Size
96KB
# I/os (max)
80
Number Of Timers - General Purpose
4
Operating Supply Voltage (typ)
1.8/3.3V
Operating Supply Voltage (max)
2/3.6V
Operating Supply Voltage (min)
1.65/1.77/2.5/2.7V
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
128
Package Type
LQFP
For Use With
MCBSTR9UME - BOARD EVAL MCBSTR9 + ULINK-MEMCBSTR9U - BOARD EVAL MCBSTR9 + ULINK2MCBSTR9 - BOARD EVAL STM STR9 SERIES
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
 Details
Other names
497-9039
STR912FAW47X6

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0
Pin description
5.2
5.2.1
46/102
1
2
3
4
5
6
7
8
9
Default pin functions
During and just after reset, all pins on ports 0-9 default to high-impedance input mode until
CPU firmware assigns other functions to the pins. This initial input mode routes all pins on
ports 0-9 to be read as GPIO inputs as shown in the “Default Pin Function” column of
Table
shown in the “Default Input Function” column of
remain until CPU firmware makes other assignments. At any time, even after the CPU
assigns pins to alternate functions, the CPU may always read the state of any pin on ports
0-9 as a GPIO input. CPU firmware may assign alternate functions to port pins as shown in
columns “Alternate Input 1” or “Alternate Output 1, 2, 3” of
registers at run-time.
General notes on pin usage
Since there are no internal or programmable pull-up resistors on ports 0-9, it is advised to
pull down to ground, or pull up to VDDQ (using max. 47 K Ω resistors), all unused pins on
port 0-9. Another solution is to use the GPIO control registers to configure the unused pins
on ports 0-9 as output low level. The purpose of this is to reduce noise susceptibility, noise
generation, and minimize power consumption
All pins on ports 0 - 9 are 5V tolerant
Pins on ports 0,1,2,4,5,7,8,9 have 4 mA drive and 4mA sink. Ports 3 and 6 have 8 mA drive
and 8 mA sink.
For 8-bit non-muxed EMI operation: Port 8 is eight bits of data, ports 7 and 9 are 16 bits of
address.
For 16-bit muxed EMI operation: Ports 8 and 9 are 16 bits of muxed address and data bits,
port 7 is up to eight additional bits of high-order address
Signal polarity is programmable for interrupt request inputs, EMI_ALE, timer input capture
inputs and output compare/PWM outputs, motor control tach and emergency stop inputs,
and motor control phase outputs.
HiZ = High Impedance, V = Voltage Source, G = Ground, I/O = Input/Output
STR910FA devices do not support USB. On these devices USBDP and USBDN signals are
"Not Used" (USBDN is not connected, USBDP must be pulled up by a 1.5K ohm resistor to
VDDQ), and all functions named “USB" are not available.
STR910FA 128-pin and 144-ball devices do not support Ethernet. On these devices
PHYCLK and all functions named “MII*" are not available.
8. Simultaneously, certain port pin signals are also routed to other functional inputs as
Doc ID 13495 Rev 6
Table
8, and these pin input functions will
Table 8
by writing to control
STR91xFAxxx

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