ST10F273M-4TR3 STMicroelectronics, ST10F273M-4TR3 Datasheet - Page 170
ST10F273M-4TR3
Manufacturer Part Number
ST10F273M-4TR3
Description
MCU 16BIT 512K FLASH 144-LQFP
Manufacturer
STMicroelectronics
Series
ST10r
Datasheet
1.ST10F273M-4TR3.pdf
(182 pages)
Specifications of ST10F273M-4TR3
Core Processor
ST10
Core Size
16-Bit
Speed
40MHz
Connectivity
ASC, CAN, EBI/EMI, I²C, SSC, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
111
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
36K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 24x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
144-MQFP, 144-PQFP
Processor Series
ST10F27x
Core
ST10
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ST10F273M-4TR3
Manufacturer:
STMicroelectronics
Quantity:
10 000
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Electrical characteristics
24.8.18
170/182
CLKOUT and READY
V
Table 73.
1. These timings are given for characterization purposes only, in order to assure recognition at a specific
2. Demultiplexed bus is the worst case. For multiplexed bus 2TCL are to be added to the maximum values.
t
t
t
t
t
t
t
t
t
t
t
t
29
30
31
32
33
34
35
36
37
58
59
60
DD
Symbol
clock edge.
This adds even more time for deactivating READY. 2t
to the current bus cycle.
= 5V ± 10%, V
CC CLKOUT cycle time
CC CLKOUT high time
CC CLKOUT low time
CC CLKOUT rise time
CC CLKOUT fall time
CC
SR
SR
SR
SR
SR
SR
CLKOUT rising edge to
ALE falling edge
Synchronous READY
setup time to CLKOUT
Synchronous READY
hold time after CLKOUT
Asynchronous READY
low time
Asynchronous READY
setup time
Asynchronous READY
hold time
Async. READY hold time
after RD, WR high
(Demultiplexed bus)
CLKOUT and READY timings
Parameter
SS
(1)
(1)
= 0V, T
(2)
A
= -40 to + 125°C, CL = 50pF
– 2 + t
Min
25
10
17
35
17
9
–
–
2
2
0
f
TCL = 12.5ns
CPU
A
A
= 40 MHz
and t
2t
A
8 + t
Max
+ t
C
25
–
–
4
4
–
–
–
–
–
refer to the next following bus cycle, t
C
A
+ t
F
2TCL + 10
TCL – 3.5
TCL – 2.5
1/2 TCL = 1 to 40 MHz
– 2 + t
2TCL
Variable CPU clock
Min
17
17
–
–
2
2
0
A
2t
A
2TCL
8 + t
Max
+ t
–
–
4
4
–
–
–
–
–
ST10F273M
C
A
+ t
F
refers
F
Unit
ns
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