ST10F273M-4TR3 STMicroelectronics, ST10F273M-4TR3 Datasheet - Page 176

• Manufacturer Part Number: ST10F273M-4TR3
• Description: MCU 16BIT 512K FLASH 144-LQFP
• Manufacturer: STMicroelectronics
• Series: ST10r

Specifications of ST10F273M-4TR3

• Core Processor: ST10
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: ASC, CAN, EBI/EMI, I²C, SSC, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 111
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 36K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 24x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 144-MQFP, 144-PQFP
• Processor Series: ST10F27x
• Core: ST10
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Electrical characteristics
Table 76.
1. When 40 MHz CPU clock is used the maximum baudrate cannot be higher than 6.6Mbaud (<SSCBR> = ‘2h’) due to the
2. Formula for SSC Clock Cycle time: t
176/182
t
t
317
318
Symbol
limited granularity of <SSCBR>. Value ‘1h’ for <SSCBR> may be used only with CPU clock lower than 32 MHz (after
checking that resulting timings are suitable for the master).
Where <SSCBR> represents the content of the SSC Baudrate register, taken as unsigned 16-bit integer.
Minimum limit allowed for t
SR
SR
Read data setup time before latch
edge, phase error detection off
(SSCPEN = 0)
Read data hold time after latch
edge, phase error detection off
(SSCPEN = 0)
SSC slave mode timings (continued)
Figure 63. SSC slave timing
1. The phase and polarity of shift and latch edge of SCLK is programmable. This figure uses the leading clock
2. The bit timing is repeated for all bits to be transmitted or received.
SCLK
MRST
MTSR
edge as shift edge (drawn in bold), with latch on trailing edge (SSCPH = 0b), Idle clock line is low, leading
clock edge is low-to-high transition (SSCPO = 0b).
Parameter
(1)
310
is 150ns (corresponding to 6.6Mbaud).
t
315
310
t
1st in bit
317
= 4 TCL * (<SSCBR> + 1)
1st out bit
t
310
t
318
Max. baudrate 6.6 Mbaud
t
t
314
315
t
311
(<SSCBR> = 0002h)
Min
31
@ f
6
2nd out bit
2nd in bit
t
CPU
312
= 40 MHz
t
t
316
313
Max
–
–
(2)
(1)
(<SSCBR> = 0001h - FFFFh)
2TCL + 6
t
315
Min
Variable baudrate
6
Last in bit
t
317
Last out bit
t
318
Max
–
–
ST10F273M
Unit
ns
ns