ST10F273M-4TR3 STMicroelectronics, ST10F273M-4TR3 Datasheet - Page 171

• Manufacturer Part Number: ST10F273M-4TR3
• Description: MCU 16BIT 512K FLASH 144-LQFP
• Manufacturer: STMicroelectronics
• Series: ST10r

Specifications of ST10F273M-4TR3

• Core Processor: ST10
• Core Size: 16-Bit
• Speed: 40MHz
• Connectivity: ASC, CAN, EBI/EMI, I²C, SSC, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 111
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 36K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 24x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 144-MQFP, 144-PQFP
• Processor Series: ST10F27x
• Core: ST10
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

ST10F273M
24.8.19
Figure 59. CLKOUT and READY
1. Cycle as programmed, including MCTC wait states (Example shows 0 MCTC WS).
2. The leading edge of the respective command depends on RW-delay.
3. READY sampled HIGH at this sampling point generates a READY controlled wait state, READY sampled
4. READY may be deactivated in response to the trailing (rising) edge of the corresponding command (RD or
5. If the Asynchronous READY signal does not fulfill the indicated setup and hold times with respect to
6. Multiplexed bus modes have a MUX wait state added after a bus cycle, and an additional MTTC wait state
7. The next external bus cycle may start here.
External bus arbitration
V
Table 74.
Symbol
t
t
t
61
62
63
DD
LOW at this sampling point terminates the currently running bus cycle.
WR).
CLKOUT (for example, because CLKOUT is not enabled), it must fulfill t
synchronized. This is guaranteed, if READY is removed in response to the command (see Note 4).
may be inserted here.
For a multiplexed bus with MTTC wait state this delay is two CLKOUT cycles, for a demultiplexed bus
without MTTC wait state this delay is zero.
= 5V ± 10%, V
SR HOLD input setup time to CLKOUT
CC
CC
CLKOUT
ALE
RD, WR
Synchronous
READY
Asynchronous
READY
CLKOUT to HLDA high
or BREQ low delay
CLKOUT to HLDA low
or BREQ high delay
External bus arbitration timings
SS
Parameter
= 0V, T
t
t
58
32
(3)
A
t
t
t
59
30
34
= -40 to +125°C, C
Running cycle
(2)
t
t
33
31
t
t
35
58
(3)
t
37
(3)
t
t
36
59
(1)
18.5
Min
f
t
(5)
TCL = 12.5ns
29
CPU
–
–
L
t
35
= 50pF
= 40 MHz
wait state
READY
(3)
t
36
Max
12.5
12.5
–
37
in order to be safely
MUX / Tri-state
t
60
1/2 TCL = 1 to 40 MHz
Electrical characteristics
Variable CPU clock
(4)
18.5
Min
–
–
(6)
(6)
(7)
Max
12.5
12.5
–
171/182
Unit
ns
ns
ns