S9S08SG4E2MTG Freescale Semiconductor, S9S08SG4E2MTG Datasheet - Page 167
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S9S08SG4E2MTG
Manufacturer Part Number
S9S08SG4E2MTG
Description
MCU 4K FLASH 16-TSSOP
Manufacturer
Freescale Semiconductor
Series
HCS08r
Datasheet
1.S9S08SG4E2CSC.pdf
(316 pages)
Specifications of S9S08SG4E2MTG
Core Processor
HCS08
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, LIN, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
12
Program Memory Size
4KB (4K x 8)
Program Memory Type
FLASH
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
16-TSSOP
Processor Series
S08SG
Core
HCS08
Data Bus Width
8 bit
Mounting Style
SMD/SMT
3rd Party Development Tools
EWS08
Development Tools By Supplier
DEMO9S08SG32, DEMO9S08SG32AUTO, DEMO9S08SG8, DEMO9S08SG8AUTO
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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11.3.4
Freescale Semiconductor
Reset
BUSY
ARBL
RXAK
Field
IAAS
SRW
IICIF
TCF
7
6
5
4
2
1
0
W
R
IIC Status Register (IICS)
TCF
Transfer Complete Flag. This bit is set on the completion of a byte transfer. This bit is only valid during or
immediately following a transfer to the IIC module or from the IIC module.The TCF bit is cleared by reading the
IICD register in receive mode or writing to the IICD in transmit mode.
0 Transfer in progress
1 Transfer complete
Addressed as a Slave. The IAAS bit is set when the calling address matches the programmed slave address
or when the GCAEN bit is set and a general call is received. Writing the IICC register clears this bit.
0 Not addressed
1 Addressed as a slave
Bus Busy. The BUSY bit indicates the status of the bus regardless of slave or master mode. The BUSY bit is
set when a start signal is detected and cleared when a stop signal is detected.
0 Bus is idle
1 Bus is busy
Arbitration Lost. This bit is set by hardware when the arbitration procedure is lost. The ARBL bit must be cleared
by software by writing a 1 to it.
0 Standard bus operation
1 Loss of arbitration
Slave Read/Write. When addressed as a slave, the SRW bit indicates the value of the R/W command bit of the
calling address sent to the master.
0 Slave receive, master writing to slave
1 Slave transmit, master reading from slave
IIC Interrupt Flag. The IICIF bit is set when an interrupt is pending. This bit must be cleared by software, by
writing a 1 to it in the interrupt routine. One of the following events can set the IICIF bit:
0 No interrupt pending
1 Interrupt pending
Receive Acknowledge. When the RXAK bit is low, it indicates an acknowledge signal has been received after
the completion of one byte of data transmission on the bus. If the RXAK bit is high it means that no acknowledge
signal is detected.
0 Acknowledge received
1 No acknowledge received
1
7
• One byte transfer completes
• Match of slave address to calling address
• Arbitration lost
= Unimplemented or Reserved
IAAS
0
6
MC9S08SG8 MCU Series Data Sheet, Rev. 6
Figure 11-6. IIC Status Register (IICS)
Table 11-7. IICS Field Descriptions
BUSY
0
5
ARBL
0
4
Description
3
0
0
Chapter 11 Inter-Integrated Circuit (S08IICV2)
SRW
0
2
IICIF
0
1
RXAK
0
0
167
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