MC9S08JM8CGT Freescale Semiconductor, MC9S08JM8CGT Datasheet - Page 281

• Manufacturer Part Number: MC9S08JM8CGT
• Description: MCU 8BIT 8K FLASH 48-QFN
• Manufacturer: Freescale Semiconductor
• Series: HCS08r

Specifications of MC9S08JM8CGT

• Core Processor: HCS08
• Core Size: 8-Bit
• Speed: 48MHz
• Connectivity: I²C, LIN, SCI, SPI, USB
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 37
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-QFN Exposed Pad
• Processor Series: S08JM
• Core: HCS08
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: I2C, SPI
• Maximum Clock Frequency: 48 MHz
• Number Of Programmable I/os: 37
• Number Of Timers: 2
• Operating Supply Voltage: 2.7 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWS08
• Development Tools By Supplier: DEMOJM, DEMOJMSKT, DEMOFLEXISJMSD, DEMO9S08JM16
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• Package: 48QFN EP
• Family Name: HCS08
• Maximum Speed: 48 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

16.3.5
These read/write registers contain the captured TPM counter value of the input capture function or the
output compare value for the output compare or PWM functions. The channel registers are cleared by
reset.
In input capture mode, reading either byte (TPMxCnVH or TPMxCnVL) latches the contents of both bytes
into a buffer where they remain latched until the other half is read. This latching mechanism also resets
Freescale Semiconductor
Reset
Reset
W
W
R
R
Bit 15
Bit 7
TPM Channel Value Registers (TPMxCnVH:TPMxCnVL)
0
0
7
7
CPWMS
0
1
Figure 16-13. TPM Channel Value Register High (TPMxCnVH)
Figure 16-14. TPM Channel Value Register Low (TPMxCnVL)
14
MSnB:MSnA
0
6
0
6
6
XX
1X
00
01
Table 16-6. Mode, Edge, and Level Selection
MC9S08JM16 Series Data Sheet, Rev. 2
13
5
0
5
5
0
ELSnB:ELSnA
X1
X1
01
10
11
01
10
11
10
10
12
0
4
0
4
4
Output compare
Center-aligned
Edge-aligned
Input capture
Mode
PWM
PWM
11
0
3
0
3
3
Capture on falling edge
Capture on rising edge
Set output on compare
High-true pulses (clear
High-true pulses (clear
output on compare-up)
output on compare-up)
10
0
2
0
2
2
Low-true pulses (set
Low-true pulses (set
Capture on rising or
output on compare)
output on compare)
Toggle output on
Clear output on
Configuration
falling edge
compare
compare
only
only
1
9
0
1
1
0
Bit 8
Bit 0
0
0
0
0
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