MC9S08JM8CGT Freescale Semiconductor, MC9S08JM8CGT Datasheet - Page 81

• Manufacturer Part Number: MC9S08JM8CGT
• Description: MCU 8BIT 8K FLASH 48-QFN
• Manufacturer: Freescale Semiconductor
• Series: HCS08r

Specifications of MC9S08JM8CGT

• Core Processor: HCS08
• Core Size: 8-Bit
• Speed: 48MHz
• Connectivity: I²C, LIN, SCI, SPI, USB
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 37
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-QFN Exposed Pad
• Processor Series: S08JM
• Core: HCS08
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: I2C, SPI
• Maximum Clock Frequency: 48 MHz
• Number Of Programmable I/os: 37
• Number Of Timers: 2
• Operating Supply Voltage: 2.7 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWS08
• Development Tools By Supplier: DEMOJM, DEMOJMSKT, DEMOFLEXISJMSD, DEMO9S08JM16
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 8 Channel
• Package: 48QFN EP
• Family Name: HCS08
• Maximum Speed: 48 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

6.5.2
In addition to the I/O control, port A pins are controlled by the registers listed below.
Freescale Semiconductor
PTAPE[5,0]
PTASE[5,0]
Reset
Reset
Reset
Field
Field
5,0
5,0
W
W
W
R
R
R
Port A Pin Control Registers (PTAPE, PTASE, PTADS)
Internal Pullup Enable for Port A Bits — Each of these control bits determines if the internal pullup device is
enabled for the associated PTA pin. For port A pins that are configured as outputs, these bits have no effect and
the internal pullup devices are disabled.
0 Internal pullup device disabled for port A bit n.
1 Internal pullup device enabled for port A bit n.
Output Slew Rate Control Enable for Port A Bits — Each of these control bits determine whether output slew
rate control is enabled for the associated PTA pin. For port A pins that are configured as inputs, these bits have
no effect.
0 Output slew rate control disabled for port A bit n.
1 Output slew rate control enabled for port A bit n.
0
0
0
7
7
7
Figure 6-5. Output Slew Rate Control Enable for Port A (PTASE)
Figure 6-6. Output Drive Strength Selection for Port A (PTASE)
0
0
0
6
6
6
Figure 6-4. Internal Pullup Enable for Port A (PTAPE)
Table 6-3. PTADD Register Field Descriptions
Table 6-4. PTASE Register Field Descriptions
PTAPE5
PTASE5
PTADS5
MC9S08JM16 Series Data Sheet, Rev. 2
0
1
0
5
5
5
0
1
0
4
4
4
Description
Description
3
0
3
1
3
0
0
1
0
2
2
2
Chapter 6 Parallel Input/Output
0
1
0
1
1
1
PTAPE0
PTASE0
PTADS0
0
1
0
0
0
0
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