MC9S08AC48MFDE Freescale Semiconductor, MC9S08AC48MFDE Datasheet - Page 105
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MC9S08AC48MFDE
Manufacturer Part Number
MC9S08AC48MFDE
Description
MCU 8BIT 48K FLASH 48-QFN
Manufacturer
Freescale Semiconductor
Series
HCS08r
Datasheet
1.MC9S08AC60CFJE.pdf
(348 pages)
Specifications of MC9S08AC48MFDE
Core Processor
HCS08
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
38
Program Memory Size
48KB (48K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
48-QFN Exposed Pad
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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6.6.14
In addition to the I/O control, port G pins are controlled by the registers listed below.
Freescale Semiconductor
PTGPE[6:0]
PTGSE[6:0]
Reset
Reset
Field
Field
6:0
6:0
W
W
R
R
Port G Pin Control Registers (PTGPE, PTGSE, PTGDS)
Internal Pullup Enable for Port G Bits — Each of these control bits determines if the internal pullup device is
enabled for the associated PTG pin. For port G pins that are configured as outputs, these bits have no effect and
the internal pullup devices are disabled.
0 Internal pullup device disabled for port G bit n.
1 Internal pullup device enabled for port G bit n.
Output Slew Rate Control Enable for Port G Bits— Each of these control bits determine whether output slew
rate control is enabled for the associated PTG pin. For port G pins that are configured as inputs, these bits have
no effect.
0 Output slew rate control disabled for port G bit n.
1 Output slew rate control enabled for port G bit n.
0
0
0
0
7
7
Figure 6-35. Output Slew Rate Control Enable for Port G Bits (PTGSE)
PTGPE6
PTGSE6
Figure 6-34. Internal Pullup Enable for Port G Bits (PTGPE)
0
0
6
6
Table 6-34. PTGSE Register Field Descriptions
Table 6-33. PTGPE Register Field Descriptions
PTGPE5
PTGSE5
MC9S08AC60 Series Data Sheet, Rev. 2
0
0
5
5
PTGPE4
PTGSE4
0
0
4
4
Description
Description
PTGPE3
PTGSE3
3
0
3
0
PTGPE2
PTGSE2
0
0
2
2
Chapter 6 Parallel Input/Output
PTGPE1
PTGSE1
0
0
1
1
PTGPE0
PTGSE0
0
0
0
0
105
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