MC9S08AC48MFDE Freescale Semiconductor, MC9S08AC48MFDE Datasheet - Page 159
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MC9S08AC48MFDE
Manufacturer Part Number
MC9S08AC48MFDE
Description
MCU 8BIT 48K FLASH 48-QFN
Manufacturer
Freescale Semiconductor
Series
HCS08r
Datasheet
1.MC9S08AC60CFJE.pdf
(348 pages)
Specifications of MC9S08AC48MFDE
Core Processor
HCS08
Core Size
8-Bit
Speed
40MHz
Connectivity
I²C, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
38
Program Memory Size
48KB (48K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
48-QFN Exposed Pad
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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9.7.2.4
The ADC quantizes the ideal straight-line transfer function into 1024 steps (in 10-bit mode). Each step
ideally has the same height (1 code) and width. The width is defined as the delta between the transition
points to one code and the next. The ideal code width for an N bit converter (in this case N can be 8 or 10),
defined as 1
There is an inherent quantization error due to the digitization of the result. For 8-bit or 10-bit conversions
the code will transition when the voltage is at the midpoint between the points where the straight line
transfer function is exactly represented by the actual transfer function. Therefore, the quantization error
will be ± 1/2
conversion is only 1/2
9.7.2.5
The ADC may also exhibit non-linearity of several forms. Every effort has been made to reduce these
errors but the system should be aware of them because they affect overall accuracy. These errors are:
9.7.2.6
Analog-to-digital converters are susceptible to three special forms of error. These are code jitter,
non-monotonicity, and missing codes.
Code jitter is when, at certain points, a given input voltage converts to one of two values when sampled
repeatedly. Ideally, when the input voltage is infinitesimally smaller than the transition voltage, the
Freescale Semiconductor
•
•
•
•
•
•
•
Average the result by converting the analog input many times in succession and dividing the sum
of the results. Four samples are required to eliminate the effect of a 1
Reduce the effect of synchronous noise by operating off the asynchronous clock (ADACK) and
averaging. Noise that is synchronous to ADCK cannot be averaged out.
Zero-scale error (E
the actual code width of the first conversion and the ideal code width (1/2
conversion is $001, then the difference between the actual $001 code width and its ideal (1
used.
Full-scale error (E
the last conversion and the ideal code width (1.5
difference between the actual $3FE code width and its ideal (1
Differential non-linearity (DNL) — This error is defined as the worst-case difference between the
actual code width and the ideal code width for all conversions.
Integral non-linearity (INL) — This error is defined as the highest-value the (absolute value of the)
running sum of DNL achieves. More simply, this is the worst-case difference of the actual
transition voltage to a given code and its corresponding ideal transition voltage, for all codes.
Total unadjusted error (TUE) — This error is defined as the difference between the actual transfer
function and the ideal straight-line transfer function, and therefore includes all forms of error.
LSB
LSB
Code Width and Quantization Error
Linearity Errors
Code Jitter, Non-Monotonicity and Missing Codes
, is:
in 8- or 10-bit mode. As a consequence, however, the code width of the first ($000)
LSB
FS
and the code width of the last ($FF or $3FF) is 1.5
ZS
) — This error is defined as the difference between the actual code width of
) (sometimes called offset) — This error is defined as the difference between
MC9S08AC60 Series Data Sheet, Rev. 2
1
LSB
= (V
REFH
- V
REFL
LSB
) / 2
). Note, if the last conversion is $3FE, then the
N
Chapter 9 Analog-to-Digital Converter (S08ADC10V1)
LSB
) is used.
LSB
LSB
, one-time error.
.
LSB
). Note, if the first
Eqn. 9-2
LSB
) is
159
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