MC9S08GT8ACFBE Freescale Semiconductor, MC9S08GT8ACFBE Datasheet - Page 168

• Manufacturer Part Number: MC9S08GT8ACFBE
• Description: IC MCU 8K FLASH 1K RAM 44-QFP
• Manufacturer: Freescale Semiconductor
• Series: HCS08r

Specifications of MC9S08GT8ACFBE

• Core Processor: HCS08
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 36
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-QFP
• Processor Series: S08GT
• Core: HCS08
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: I2C/SCI/SPI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 36
• Operating Supply Voltage: 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWS08
• Development Tools By Supplier: M68EVB908GB60E, M68DEMO908GB60E
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• For Use With: M68DEMO908GB60E - BOARD DEMO MC9S08GB60M68EVB908GB60E - BOARD EVAL FOR MC9S08GB60
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Timer/Pulse-Width Modulator (S08TPMV2)
10.5.3
The meaning of channel interrupts depends on the current mode of the channel (input capture, output
compare, edge-aligned PWM, or center-aligned PWM).
When a channel is configured as an input capture channel, the ELSnB:ELSnA control bits select rising
edges, falling edges, any edge, or no edge (off) as the edge that triggers an input capture event. When the
selected edge is detected, the interrupt flag is set. The flag is cleared by the 2-step sequence described in
Section 10.5.1, “Clearing Timer Interrupt
When a channel is configured as an output compare channel, the interrupt flag is set each time the main
timer counter matches the 16-bit value in the channel value register. The flag is cleared by the 2-step
sequence described in
10.5.4
For channels that are configured for PWM operation, there are two possibilities:
The flag is cleared by the 2-step sequence described in
168
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•
When the channel is configured for edge-aligned PWM, the channel flag is set when the timer
counter matches the channel value register that marks the end of the active duty cycle period.
When the channel is configured for center-aligned PWM, the timer count matches the channel
value register twice during each PWM cycle. In this CPWM case, the channel flag is set at the start
and at the end of the active duty cycle, which are the times when the timer counter matches the
channel value register.
Channel Event Interrupt Description
PWM End-of-Duty-Cycle Events
Section 10.5.1, “Clearing Timer Interrupt
MC9S08GT16A/GT8A Data Sheet, Rev. 1
Flags.”
Section 10.5.1, “Clearing Timer Interrupt
Flags.”
Freescale Semiconductor
Flags.”