MC9S08GT8ACFBE Freescale Semiconductor, MC9S08GT8ACFBE Datasheet - Page 31

• Manufacturer Part Number: MC9S08GT8ACFBE
• Description: IC MCU 8K FLASH 1K RAM 44-QFP
• Manufacturer: Freescale Semiconductor
• Series: HCS08r

Specifications of MC9S08GT8ACFBE

• Core Processor: HCS08
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 36
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-QFP
• Processor Series: S08GT
• Core: HCS08
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: I2C/SCI/SPI
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 36
• Operating Supply Voltage: 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWS08
• Development Tools By Supplier: M68EVB908GB60E, M68DEMO908GB60E
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• For Use With: M68DEMO908GB60E - BOARD DEMO MC9S08GB60M68EVB908GB60E - BOARD EVAL FOR MC9S08GB60
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

When an on-chip peripheral system is controlling a pin, data direction control bits still determine what is
read from port data registers even though the peripheral module controls the pin direction by controlling
the enable for the pin’s output buffer. See
Pullup enable bits for each input pin control whether on-chip pullup devices are enabled whenever the pin
is acting as an input even if it is being controlled by an on-chip peripheral module. When the PTA7–PTA4
pins are controlled by the KBI module and are configured for rising-edge/high-level sensitivity, the pullup
enable control bits enable pulldown devices rather than pullup devices. Similarly, when IRQ is configured
as the IRQ input and is set to detect rising edges, the pullup enable control bit enables a pulldown device
rather than a pullup device.
2.3.7
Table 2-2
common pin interfaces are hardwired to internal circuits.
Freescale Semiconductor
PTA0/KBIP0
PTA1/KBIP1
PTA2/KBIP2
PTA3/KBIP3
PTA4/KBIP4
PTA5/KBIP5
PTA6/KBIP6
PTA7/KBIP7
PTB0/ADP0
PTB1/ADP1
PTB2/ADP2
RESET
V
Name
V
V
V
summarizes I/O pin characteristics. These characteristics are determined by the way the
V
V
IRQ
Pin
DDAD
SSAD
REFH
REFL
Signal Properties Summary
DD
SS
Dir
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
High Current
MC9S08GT16A/GT8A Data Sheet, Rev. 1
Pin
—
—
—
—
—
—
—
Table 2-2. Signal Properties
Y
N
N
N
N
N
N
N
N
N
N
N
Chapter 6, “Parallel
Output
Slew
SWC
SWC
SWC
SWC
SWC
SWC
SWC
SWC
SWC
SWC
SWC
—
—
—
—
—
—
—
N
1
Pull-Up
SWC
SWC
SWC
SWC
SWC
SWC
SWC
SWC
SWC
SWC
SWC
Input/Output,” for details.
—
—
—
—
—
—
Y
Y
2
The 48-pin QFN package has two V
— V
Pin contains integrated pullup.
IRQPE must be set to enable IRQ function.
IRQ does not have a clamp diode to V
IRQ should not be driven above V
Pullup/pulldown active when IRQ pin
function enabled. Pullup forced on when
IRQ enabled for falling edges; pulldown
forced on when IRQ enabled for rising
edges.
Pullup/pulldown active when KBI pin
function enabled. Pullup forced on when
KBIPx enabled for falling edges; pulldown
forced on when KBIPx enabled for rising
edges.
SS1
and V
SS2
Comments
.
Pins and Connections
DD
SS
.
DD
pins
31
.