MC56F8011VFAE Freescale Semiconductor, MC56F8011VFAE Datasheet - Page 9

• Manufacturer Part Number: MC56F8011VFAE
• Description: IC DIGITAL SIGNAL CTLR 32-LQFP
• Manufacturer: Freescale Semiconductor
• Series: 56F8xxxr

Specifications of MC56F8011VFAE

• Core Processor: 56800
• Core Size: 16-Bit
• Speed: 32MHz
• Connectivity: I²C, SCI, SPI
• Peripherals: POR, PWM, WDT
• Number Of I /o: 26
• Program Memory Size: 12KB (6K x 16)
• Program Memory Type: FLASH
• Ram Size: 1K x 16
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 6x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 32-LQFP
• Product: DSCs
• Data Bus Width: 16 bit
• Processor Series: MC56F80xx
• Core: 56800E
• Numeric And Arithmetic Format: Fixed-Point
• Device Million Instructions Per Second: 32 MIPs
• Maximum Clock Frequency: 32 MHz
• Number Of Programmable I/os: 26
• Data Ram Size: 2 KB
• Operating Supply Voltage: 3.3 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: MC56F8037EVM, DEMO56F8014-EE, DEMO56F8013-EE
• Interface Type: SCI, SPI, I2C
• Minimum Operating Temperature: - 40 C
• For Use With: CPA56F8013 - BOARD SOCKET FOR MC56F8013APMOTOR56F8000E - KIT DEMO MOTOR CTRL SYSTEM
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

1.3 Award-Winning Development Environment
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1.4 Architecture Block Diagram
The 56F8013/56F8011’s architecture is shown in
illustrates how the 56800E system buses communicate with internal memories and the IPBus Bridge and
the internal connections between each unit of the 56800E core.
control blocks connected to the IPBus Bridge.
The figures do not show the on-board regulator and power and ground signals. Please see
Signal/Connection
1.5 Synchronize ADC with PWM
ADC conversion can be synchronized with PWM module via Quad Timer channel 2 and 3 if needed.
Internally, the PWM synch signal, which is generated at every PWM reload, can be connected to the timer
channel 3 input and the timer channel 2 and 3 outputs are connected to ADC sync inputs. Timer channel
3 output is connected to SYNC0 and Timer channel 2 is connected to SYNC1. The setting is controlled by
TC3_INP bit in the SIM Control Register; see
SYNC0 is the master ADC sync input is used to trigger both ADCA and ADCB in sequence and parallel
mode. SYNC1 is used to trigger ADCB in parallel independent mode, while SYNC0 is used to trigger
ADCA. See 56F801X Peripheral Reference Manual for additional information.
1.6 Multiple Frequency PWM
When both PWM channels of a complementary pair in software control mode and software control bits
are set to 1, each complementary PWM signal pair—PWM 0 and 1; PWM 2 and 3; PWM 4 and 5—can
select a PWM source of one of following sources that enables each PWM pair to output different frequency
PWM signal.
Freescale Semiconductor
•
•
External GPIO input:
— GPIOB2 input can be used to drive PWM 0 and 1
— GPIOB3 input can be used to drive PWM 2 and 3
— GPIOB4 input can be used to drive PWM 4 and 5
Quad Timer output:
— Timer0 output can be used to drive PWM 0 and 1
TM
Descriptions, to see which signals are multiplexed with those of other peripherals.
(PE) provides a Rapid Application Design (RAD) tool that combines easy-to-use
56F8013/56F8011 Data Sheet, Rev. 12
Section
Figure 1-3
Figure
6.3.1.
1-1,
details how the device’s I/O pins are muxed.
Figure
Figure 1-2
1-2, and
Award-Winning Development Environment
shows the peripherals and
Figure
1-3.
Figure 1-1
Part 2,
9