MC9S12P96MFT Freescale Semiconductor, MC9S12P96MFT Datasheet - Page 266
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MC9S12P96MFT
Manufacturer Part Number
MC9S12P96MFT
Description
MCU 16BIT 96K FLASH 48-QFN
Manufacturer
Freescale Semiconductor
Series
HCS12r
Datasheet
1.S9S12P32J0MFT.pdf
(566 pages)
Specifications of MC9S12P96MFT
Core Processor
HCS12
Core Size
16-Bit
Speed
32MHz
Connectivity
CAN, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
34
Program Memory Size
96KB (96K x 8)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
6K x 8
Voltage - Supply (vcc/vdd)
1.72 V ~ 5.5 V
Data Converters
A/D 10x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
48-QFN Exposed Pad
Processor Series
S12P
Core
HCS12
3rd Party Development Tools
EWHCS12
Development Tools By Supplier
KIT33812ECUEVME, DEMO9S12PFAME
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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Freescale’s Scalable Controller Area Network (S12MSCANV3)
1. Read: Anytime
8.3.2.8
This register contains the interrupt enable bits for the transmit buffer empty interrupt flags.
266
Module Base + 0x0006
Module Base + 0x0007
Write: Anytime when not in initialization mode; write of 1 clears flag, write of 0 is ignored
TXE[2:0]
Field
2-0
Reset:
Reset:
W
W
R
R
Transmitter Buffer Empty — This flag indicates that the associated transmit message buffer is empty, and thus
not scheduled for transmission. The CPU must clear the flag after a message is set up in the transmit buffer and
is due for transmission. The MSCAN sets the flag after the message is sent successfully. The flag is also set by
the MSCAN when the transmission request is successfully aborted due to a pending abort request (see
Section 8.3.2.9, “MSCAN Transmitter Message Abort Request Register
interrupt is pending while this flag is set.
Clearing a TXEx flag also clears the corresponding ABTAKx (see
Message Abort Acknowledge Register
is cleared (see
When listen-mode is active (see
cannot be cleared and no transmission is started.
Read and write accesses to the transmit buffer will be blocked, if the corresponding TXEx bit is cleared
(TXEx = 0) and the buffer is scheduled for transmission.
0 The associated message buffer is full (loaded with a message due for transmission)
1 The associated message buffer is empty (not scheduled)
MSCAN Transmitter Interrupt Enable Register (CANTIER)
The CANTFLG register is held in the reset state when the initialization
mode is active (INITRQ = 1 and INITAK = 1). This register is writable when
not in initialization mode (INITRQ = 0 and INITAK = 0).
0
0
0
0
7
7
Figure 8-11. MSCAN Transmitter Interrupt Enable Register (CANTIER)
Figure 8-10. MSCAN Transmitter Flag Register (CANTFLG)
Section 8.3.2.9, “MSCAN Transmitter Message Abort Request Register
= Unimplemented
= Unimplemented
Table 8-13. CANTFLG Register Field Descriptions
0
0
0
0
6
6
S12P-Family Reference Manual, Rev. 1.13
Section 8.3.2.2, “MSCAN Control Register 1
0
0
0
0
5
5
(CANTAAK)”). When a TXEx flag is set, the corresponding ABTRQx bit
NOTE
0
0
0
0
4
4
Description
3
0
0
3
0
0
Section 8.3.2.10, “MSCAN Transmitter
(CANTARQ)”). If not masked, a transmit
TXEIE2
TXE2
1
0
2
2
(CANCTL1)”) the TXEx flags
Access: User read/write
Access: User read/write
Freescale Semiconductor
TXEIE1
(CANTARQ)”).
TXE1
1
0
1
1
TXEIE0
TXE0
1
0
0
0
(1)
(1)
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