MC9S08DV96CLF Freescale Semiconductor, MC9S08DV96CLF Datasheet - Page 218

• Manufacturer Part Number: MC9S08DV96CLF
• Description: MCU 8BIT 96K FLASH 48-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS08r

Specifications of MC9S08DV96CLF

• Core Processor: HCS08
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: CAN, I²C, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 39
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 16x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-LQFP
• Processor Series: S08DV
• Core: HCS08
• Data Bus Width: 8 bit
• Data Ram Size: 4 KB
• Interface Type: CAN, I2C, SPI, UART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 87
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWS08
• Development Tools By Supplier: DEMO9S08DZ60
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 24 Channel
• A/d Bit Size: 12 bit
• A/d Channels Available: 24
• Height: 1.4 mm
• Length: 7 mm
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 2.7 V
• Width: 7 mm
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Chapter 10 Analog-to-Digital Converter (S08ADC12V1)
10.3.8
218
The pin control registers disable the I/O port control of MCU pins used as analog inputs. APCTL1 is
ADICLK
MODE
Field
3:2
1:0
Pin Control 1 Register (APCTL1)
Conversion Mode Selection. MODE bits are used to select between 12-, 10-, or 8-bit operation. See
Input Clock Select. ADICLK bits select the input clock source to generate the internal clock ADCK. See
Table
10-9.
Table 10-6. ADCCFG Register Field Descriptions (continued)
ADICLK
MODE
ADIV
00
01
10
11
00
01
10
11
00
01
10
11
MC9S08DZ128 Series Data Sheet, Rev. 1
8-bit conversion (N=8)
12-bit conversion (N=12)
10-bit conversion (N=10)
Reserved
Bus clock
Bus clock divided by 2
Alternate clock (ALTCLK)
Asynchronous clock (ADACK)
Table 10-7. Clock Divide Select
Table 10-8. Conversion Modes
Table 10-9. Input Clock Select
Divide Ratio
1
2
4
8
Selected Clock Source
Mode Description
Description
Input clock ÷ 2
Input clock ÷ 4
Input clock ÷ 8
Clock Rate
Input clock
Freescale Semiconductor
Table
10-8.