MC9S08DV96CLF Freescale Semiconductor, MC9S08DV96CLF Datasheet - Page 401

• Manufacturer Part Number: MC9S08DV96CLF
• Description: MCU 8BIT 96K FLASH 48-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS08r

Specifications of MC9S08DV96CLF

• Core Processor: HCS08
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: CAN, I²C, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 39
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 16x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-LQFP
• Processor Series: S08DV
• Core: HCS08
• Data Bus Width: 8 bit
• Data Ram Size: 4 KB
• Interface Type: CAN, I2C, SPI, UART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 87
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWS08
• Development Tools By Supplier: DEMO9S08DZ60
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 24 Channel
• A/d Bit Size: 12 bit
• A/d Channels Available: 24
• Height: 1.4 mm
• Length: 7 mm
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 2.7 V
• Width: 7 mm
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

18.3.3.8
1
Freescale Semiconductor
end-run
Module Base + 0x0007
end-run
Bits 15–8
or non-
In the case of an end-trace to reset where DBGEN=1 and BEGIN=0, the bits in this register do not change after reset.
Bits 7–0
Reset
Field
Field
POR
W
R
1
FIFO High Data Bits — The FIFO High data bits provide access to bits [15:8] of data in the FIFO. This register
is not used in event only modes and will read a $00 for valid FIFO words.
Bit 7
FIFO Low Data Bits — The FIFO Low data bits contain the least significant byte of data in the FIFO. When
reading FIFO words, read DBGFX and DBGFH before reading DBGFL because reading DBGFL causes the
FIFO pointers to advance to the next FIFO location. In event-only modes, there is no useful information in DBGFX
and DBGFH so it is not necessary to read them before reading DBGFL.
Debug FIFO Low Register (DBGFL)
U
0
7
= Unimplemented or Reserved
Bit 6
U
0
6
Figure 18-9. Debug FIFO Low Register (DBGFL)
Table 18-10. DBGFL Field Descriptions
Table 18-9. DBGFH Field Descriptions
MC9S08DZ128 Series Data Sheet, Rev. 1
Bit 5
U
0
5
Bit 4
U
0
4
Description
Description
Bit 3
U
0
3
Chapter 18 Debug Module (S08DBGV3) (128K)
Bit 2
U
0
2
Bit 1
U
0
1
Bit 0
U
0
0
401