MC9S08DV96CLF Freescale Semiconductor, MC9S08DV96CLF Datasheet - Page 79

• Manufacturer Part Number: MC9S08DV96CLF
• Description: MCU 8BIT 96K FLASH 48-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HCS08r

Specifications of MC9S08DV96CLF

• Core Processor: HCS08
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: CAN, I²C, LIN, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 39
• Program Memory Size: 96KB (96K x 8)
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 16x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 48-LQFP
• Processor Series: S08DV
• Core: HCS08
• Data Bus Width: 8 bit
• Data Ram Size: 4 KB
• Interface Type: CAN, I2C, SPI, UART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 87
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWS08
• Development Tools By Supplier: DEMO9S08DZ60
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 12 bit, 24 Channel
• A/d Bit Size: 12 bit
• A/d Channels Available: 24
• Height: 1.4 mm
• Length: 7 mm
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 2.7 V
• Width: 7 mm
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

4.6.11.3
Freescale Semiconductor
EPGMOD
EPGSEL
KEYACC
Reset
Field
Field
SEC
1:0
5
6
5
W
R
EEPROM Sector Mode — When this bit is 0, each sector is split into two pages (4-byte mode). When this bit is
1, each sector is in a single page (8-byte mode).
0 Half of each EEPROM sector is in Page 0 and the other half is in Page 1.
1 Each sector is in a single page.
Security State Code — This 2-bit field determines the security state of the MCU as shown in
the MCU is secure, the contents of RAM, EEPROM and FLASH memory cannot be accessed by instructions
from any unsecured source including the background debug interface. SEC changes to 1:0 after successful
backdoor key entry or a successful blank check of FLASH. For more detailed information about security, refer to
Section 4.6.9,
EEPROM Page Select — This bit selects which EEPROM page is accessed in the memory map.
0 Page 0 is in foreground of memory map. Page 1 is in background and can not be accessed.
1 Page 1 is in foreground of memory map. Page 0 is in background and can not be accessed.
Enable Writing of Access Key — This bit enables writing of the backdoor comparison key. For more detailed
information about the backdoor key mechanism, refer to
0 Writes to 0xFFB0–0xFFB7 are interpreted as the start of a FLASH programming or erase command.
1 Writes to NVBACKKEY (0xFFB0–0xFFB7) are interpreted as comparison key writes.
FLASH and EEPROM Configuration Register (FCNFG)
0
0
7
Figure 4-16. FLASH and EEPROM Configuration Register (FCNFG)
= Unimplemented or Reserved
EPGSEL
“Security.”
0
6
1
Table 4-17. FCNFG Register Field Descriptions
SEC changes to 1:0 after successful backdoor key entry
or a successful blank check of FLASH.
Table 4-15. FOPT Register Field Descriptions
MC9S08DZ128 Series Data Sheet, Rev. 1
KEYACC
SEC[1:0]
0
5
0:0
0:1
1:0
1:1
Table 4-16. Security States
1
1
4
Description
Description
Section 4.6.9,
Description
unsecured
secure
secure
secure
3
0
0
1
“Security.”
0
0
2
0
0
1
Table
Chapter 4 Memory
4-16. When
1
1
0
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