MC908MR8MPE Freescale Semiconductor, MC908MR8MPE Datasheet - Page 119
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MC908MR8MPE
Manufacturer Part Number
MC908MR8MPE
Description
IC MCU 8BIT 8K FLASH 28-PDIP
Manufacturer
Freescale Semiconductor
Series
HC08r
Datasheet
1.MCHC908MR8VFAE.pdf
(372 pages)
Specifications of MC908MR8MPE
Core Processor
HC08
Core Size
8-Bit
Speed
8MHz
Connectivity
SCI
Peripherals
LVD, POR, PWM
Number Of I /o
12
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
28-DIP (0.600", 15.24mm)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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MC68HC908MR8 — Rev 4.1
Freescale Semiconductor
These conditions apply when the PLL is in automatic bandwidth control
mode:
The PLL also may operate in manual mode (AUTO = 0). Manual mode
is used by systems that do not require an indicator of the lock condition
for proper operation. Such systems typically operate well below f
and require fast startup.
These conditions apply when in manual mode:
•
•
•
•
•
•
•
•
•
•
The ACQ bit (see
read-only indicator of the mode of the filter. See
Acquisition and Tracking
The ACQ bit is set when the VCO frequency is within a certain
tolerance, ∆
a certain tolerance, ∆
Specifications
The LOCK bit is a read-only indicator of the locked state of the
PLL.
The LOCK bit is set when the VCO frequency is within a certain
tolerance, ∆
a certain tolerance, ∆
Specifications
CPU interrupts can occur if enabled (PLLIE = 1) when the PLL’s
lock condition changes, toggling the LOCK bit. See
Control
ACQ is a writable control bit that controls the mode of the filter.
Before turning on the PLL in manual mode, the ACQ bit must be
clear.
Before entering tracking mode (ACQ = 1), software must wait a
given time, t
Specifications), after turning on the PLL by setting PLLON in the
PLL control register (PCTL).
Software must wait a given time, t
before selecting the PLL as the clock source to CGMOUT
(BCS = 1).
The LOCK bit is disabled.
CPU interrupts from the CGM are disabled.
Clock Generator Module (CGM)
Register.
TRK
Lock
ACQ
, and is cleared when the VCO frequency is out of
, and is cleared when the VCO frequency is out of
for more information.
for more information.
(see
8.6.2 PLL Bandwidth Control
UNT
UNL
8.11 Acquisition/Lock Time
. See
. See
Modes.
8.11 Acquisition/Lock Time
8.11 Acquisition/Lock Time
AL
, after entering tracking mode
Clock Generator Module (CGM)
Functional Description
8.4.2.2
Register) is a
8.6.1 PLL
Technical Data
BUSMAX
119
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